Journal ArticleDOI
Optical Interposer Technology using Buried Vertical-Cavity Surface-Emitting Laser Chip and Tapered Through-Silicon Via for High-Speed Chip-to-Chip Optical Interconnection
Akihiro Noriki,Makoto Fujiwara,Kang-Wook Lee,W.-C. Jeong,Takafumi Fukushima,Tetsu Tanaka,Mitsumasa Koyanagi +6 more
TLDR
In this article, a novel optical interposer with optical interconnections is proposed for integrating three-dimensional (3D) LSI chips on this interposers, which realize precise passive alignment between the optical waveguides and the VCSEL/PD chips using two-step alignment processes consisting of cavity-assisted positioning and subsequent surface-tension-powered self-assembly with a molten solder.Abstract:
A novel optical interposer with optical interconnections is proposed for integrating three-dimensional (3D) LSI chips on this interposer. Vertical-cavity surface-emitting laser diode (VCSEL) chips and photo diode (PD) chips are buried in the optical interposer with polymeric optical waveguides. The VCSEL is 0.25 mm in width, 0.35 mm in length, and 0.15 mm in height. We realize precise passive alignment between the optical waveguides and the VCSEL/PD chips using two-step alignment processes consisting of cavity-assisted positioning and the subsequent surface-tension-powered self-assembly with a molten solder. In addition, we demonstrate the basic operation of the buried VCSEL chips in the optical interposer through tapered through-silicon vias (TSVs). The tapered TSVs are successfully formed by copper electroplating and are 64 µm in top width, 34 µm in bottom width, and 168 µm in length.read more
Citations
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Journal ArticleDOI
Three-Dimensional Hybrid Integration Technology of CMOS, MEMS, and Photonics Circuits for Optoelectronic Heterogeneous Integrated Systems
Kang-Wook Lee,Akihiro Noriki,Koji Kiyoyama,Takafumi Fukushima,Tetsu Tanaka,Mitsumasa Koyanagi +5 more
TL;DR: The basic functions of individual chips of LSI, MEMS, and photonics devices as they were integrated into the3-D optoelectronic multichip module to verify the applied 3-D hybrid integration technology.
Proceedings ArticleDOI
Development of via-last 3D integration technologies using a new temporary adhesive system
TL;DR: New via-last backside-via 3D integration technologies using a unique temporary adhesive system in which visible-light laser is employed for wafer debonding from glass carriers are developed.
Proceedings ArticleDOI
Tiny VCSEL chip self-assembly for advanced chip-to-wafer 3D and hetero integration
Takafumi Fukushima,Yuka Ito,Mariappan Murugesan,Jicheol Bea,Kang-Wook Lee,Koji Choki,Tetsu Tanaka,Mitsumasa Koyanagi +7 more
TL;DR: The VCSEL was accurately positioned, successfully emitted 850-nm light, and exhibited no degradation of the I-V characteristics, and recent progress on the hybrid integration of chip-scale photonic devices with 3D/TSV technologies for optical interconnections is presented.
References
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Journal ArticleDOI
Future system-on-silicon LSI chips
TL;DR: In this work, several vertically stacked chip layers in 3D LSI chips or 3D multichip modules (MCMs) are fabricated using a new three-dimensional integration technology to overcome future wiring connectivity crises.
Journal ArticleDOI
Terabus: Terabit/Second-Class Card-Level Optical Interconnect Technologies
Laurent Schares,Jeffrey A. Kash,Fuad E. Doany,Clint L. Schow,Christian Schuster,Daniel M. Kuchta,Petar Pepeljugoski,Jeannine M. Trewhella,Christian W. Baks,Richard A. John,L. Shan,Young H. Kwark,Russell A. Budd,Punit P. Chiniwalla,Frank R. Libsch,J. Rosner,Cornelia K. Tsang,Chirag S. Patel,Jeremy D. Schaub,Roger Dangel,Folkert Horst,Bert Jan Offrein,D. Kucharski,D. Guckenberger,S. Hegde,H. Nyikal,Chao-Kun Lin,Ashish Tandon,Gary R. Trott,M. Nystrom,David P. Bour,M.R.T. Tan,D.W. Dolfi +32 more
TL;DR: In this paper, a chip-like optoelectronic packaging structure (Optochip), assembled directly onto an organic card (Optocard), is developed for supporting terabit/second chip-to-chip data transfers over organic cards within high-performance servers, switch routers, and other intensive computing systems.
Journal ArticleDOI
Three-Dimensional Integration Technology Based on Wafer Bonding With Vertical Buried Interconnections
Mitsumasa Koyanagi,T. Nakamura,Yusuke Yamada,H. Kikuchi,Takafumi Fukushima,Tetsu Tanaka,Hiroyuki Kurino +6 more
TL;DR: In this article, a 3D shared-memory test chip with three-stacked layers was fabricated by bonding the wafers with vertical buried interconnections after thinning.
Journal ArticleDOI
New Three-Dimensional Wafer Bonding Technology Using the Adhesive Injection Method.
T. Matsumoto,Masakazu Satoh,Katsuyuki Sakuma,Hiroyuki Kurino,Nobuaki Miyakawa,H. Itani,Mitsumasa Koyanagi +6 more
TL;DR: In this paper, a new 3D wafer bonding technology using the adhesive injection method has been proposed, in order to realize a real-time micro-vision system and a real shared memory.
Journal ArticleDOI
PCB-compatible optical interconnection using 45/spl deg/-ended connection rods and via-holed waveguides
TL;DR: In this paper, a new architecture for a chip-to-chip optical interconnection system is demonstrated that can be applied in a waveguide-embedded optical printed circuit board (PCB).
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