Proceedings ArticleDOI
Optimization of on-package decoupling capacitors considering system variables
Aurora Sanna,Giovanni Graziosi +1 more
- pp 1-4
TLDR
How the package behavior can change depending on the interaction with PCB parameters is shown, and a methodology to optimize on-package decoupling taking into account the system variability is proposed.Abstract:
A key aspect of power integrity in modern electronic systems is the choice and optimization of decoupling capacitors. Traditionally, this issue has been addressed at PCB level, but the integration of discrete SMD capacitors inside BGA package substrates is becoming more and more common in complex high-speed digital devices. In the context of semiconductors industry, the on-package decoupling applied to digital microcontrollers needs to be defined, often without any clear information on system configuration. This paper shows how the package behavior can change depending on the interaction with PCB parameters, and proposes a methodology to optimize on-package decoupling taking into account the system variability.read more
Citations
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Proceedings ArticleDOI
On Decoupling Capacitor Size in GaN-Based Power Converters
TL;DR: In this article , a circuit model is developed to describe converter operation during the switching transition, and a simple empirical equation for optimal decoupling capacitor sizing is proposed, which is validated via experimental measurement of double pulse tests on a variety of hardware prototypes.
Proceedings ArticleDOI
Fatigue Life Prediction Model Development for Decoupling Capacitors
TL;DR: In this article, a predictive model was developed for decoupling capacitors that can be used to determine the number of cycles for first failure and the mean number of failures to failure during any thermal cycling conditions.
Proceedings ArticleDOI
BGA Package for DDR3 Interface – 4 vs 6 Layers Design Strategy and Electrical Performance Comparison
TL;DR: This work describes the comparative analysis between a 4-layer and a 6-layer stack-up on a BGA package designed for the same Double Data Rate 3 (DDR3) high speed interface for automotive application and shows how Power Integrity can be improved by using Surface Mounting Technology (SMT) decoupling capacitors.
Proceedings ArticleDOI
IC-package Optimization for Conducted EME Performance: Impact of Discrete Decoupling Capacitors and Parasitic Inductive Effects
Aurora Sanna,Giovanni Graziosi +1 more
TL;DR: In this paper, the authors analyzed the impact on conducted emissions of two important package parameters, parasitic inductance and integrated decoupling capacitors, and the trade-off between conducted emissions optimization and dynamic IR-drop reduction is also taken into account.
References
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Proceedings Article
Advanced modeling techniques for system-level power integrity and EMC analysis
Giovanni Graziosi,Patrice Joubert Doriol,Yamarita Villavicencio,Cristiano Forzan,Mario Rotigni,Davide Pandini +5 more
TL;DR: By reducing the power rail noise thus assuring the system PI, it is possible to significantly reduce the electromagnetic (EM) conducted emissions and a transistor-level lumped-element simulation model of the system power distribution network (PDN) is presented that allows chip, package, and PCB designers to predict the power integrity and the conducted emissions at critical chip I/O pads.
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Power integrity simulation of power delivery network system
TL;DR: This paper will discuss power integrity simulation using the 3D fullwave simulation tool CST STUDIO SUITE® to produce a clean signal for the high-speed driver by supplying a good source.
Proceedings ArticleDOI
Power integrity simulation of power delivery network system
TL;DR: This paper will discuss power integrity simulation using the 3D fullwave simulation tool CST STUDIO SUITE® to produce a clean signal for the high-speed driver by supplying a good source.
Proceedings ArticleDOI
Power Delivery Network simulation methodology including Integrated Circuit behavior
TL;DR: In this paper, a complete simulation methodology for the design of optimized power delivery network dedicated to High Speed High Density electronic board is presented, where each part of the Power Supply Circuit is modeled either in the time domain or in the frequency domain with the adequate tools available on the market.
Proceedings ArticleDOI
Simulation methodology for enhancement of power delivery network decoupling
TL;DR: In this article, the authors present the simulation methodology for optimizing the decoupling network of an integrated circuit like a processor or a Field Programmable Gate Array (FPGA) by correlating simulation results with measurement for S parameters analysis of bare PCB and the PCB associated with decoupled capacitors thanks to a dedicated test vehicle equipped with SMA connectors.