Optimization of process parameter variation in 45nm p-channel MOSFET using L 18 orthogonal array

TLDR: In this article, orthogonal array of L 18 in Taguchi method was used to optimize the process parameters variance on threshold voltage (V TH ) in 45nm p-channel MOSFET.

Abstract: In this study, orthogonal array of L 18 in Taguchi method was used to optimize the process parameters variance on threshold voltage (V TH ) in 45nm p-channel Metal Oxide Semiconductor Field Effect Transistor (MOSFET) device. The signal-to-noise (S/N) ratio and analysis of variance (ANOVA) are employed to study the performance characteristics of the PMOS device. There are eight process parameters (control factors) were varied for 2 and 3 levels to performed 18 experiments. Whereas, the two noise factors were varied for 2 levels to get four readings of V TH for every row of experiment. V TH results were used as the evaluation variable. This work was done using TCAD simulator, consisting of a process simulator, ATHENA and device simulator, ATLAS. These two simulators were combined with L 18 Orthogonal Array to aid in design and optimize the process parameters. The predicted values of the process parameters were verified successfully with ATHENA and ATLAS's simulator. In PMOS device, V TH implant dose (26%) and compensate implant dose (26%) were the major factors affecting the threshold voltage. While S/D Implant was identified as an adjustment factor in PMOS device. These adjustment factors have been used to get the nominal values of threshold voltage for PMOS device closer to −0.289V.