Journal ArticleDOI
Designing reliable systems from unreliable components: the challenges of transistor variability and degradation
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This article discusses effects of variability in transistor performance and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.Abstract:
As technology scales, variability in transistor performance continues to increase, making transistors less and less reliable. This creates several challenges in building reliable systems, from the unpredictability of delay to increasing leakage current. Finding solutions to these challenges require a concerted effort on the part of all the players in a system design. This article discusses these effects and proposes microarchitecture, circuit, and testing research that focuses on designing with many unreliable components (transistors) to yield reliable system designs.read more
Citations
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The Landscape of Parallel Computing Research: A View from Berkeley
Krste Asanovic,Ras Bodik,Bryan Catanzaro,Joseph Gebis,Parry Husbands,Kurt Keutzer,David A. Patterson,William Plishker,John Shalf,Samuel Williams,Katherine Yelick +10 more
TL;DR: The parallel landscape is frame with seven questions, and the following are recommended to explore the design space rapidly: • The overarching goal should be to make it easy to write programs that execute efficiently on highly parallel computing systems • The target should be 1000s of cores per chip, as these chips are built from processing elements that are the most efficient in MIPS (Million Instructions per Second) per watt, MIPS per area of silicon, and MIPS each development dollar.
Proceedings ArticleDOI
Thousand core chips: a technology perspective
TL;DR: The many-core architecture, with hundreds to thousands of small cores, is presented to deliver unprecedented compute performance in an affordable power envelope and fine grain power management, memory bandwidth, on die networks, and system resiliency are discussed.
Journal ArticleDOI
The future of microprocessors
Shekhar Borkar,Andrew A. Chien +1 more
TL;DR: Energy efficiency is the new fundamental limiter of processor performance, way beyond numbers of processors.
Proceedings ArticleDOI
Circuit Failure Prediction and Its Application to Transistor Aging
TL;DR: Simulation results using 90nm and 65nm technologies demonstrate that a new sensor design integrated inside a flip-flop enables efficient circuit failure prediction at a low cost and can significantly improve system performance by enabling close to best- case design instead of traditional worst-case design.
Patent
System comprising a semiconductor device and structure
Zvi Or-Bach,Brian Cronquist,Israel Beinglass,Jan Lodewijk de Jong,Deepak C. Sekar,Zeev Wurman +5 more
TL;DR: In this article, a system includes a semiconductor device consisting of a first single crystal silicon layer comprising first transistors, first alignment marks, and at least one metal layer overlying the first single-crystalline silicon layer.
References
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Proceedings ArticleDOI
Parameter variations and impact on circuits and microarchitecture
TL;DR: Process, voltage and temperature variations; and their impact on circuit and microarchitecture; and possible solutions to reduce the impact of parameter variations and to achieve higher frequency bins are presented.
Proceedings ArticleDOI
Razor: a low-power pipeline based on circuit-level timing speculation
Daniel J. Ernst,Nam Sung Kim,Shidhartha Das,Sanjay Pant,Rajeev R. Rao,Toan Pham,Conrad H. Ziesler,David Blaauw,Todd Austin,Krisztian Flautner,Trevor Mudge +10 more
TL;DR: A solution by which the circuit can be operated even below the ‘critical’ voltage, so that no margins are required and thus more energy can be saved.
Journal ArticleDOI
Design challenges of technology scaling
TL;DR: In this article, the authors look closely at past trends in technology scaling and how well microprocessor technology and products have met these goals and project the challenges that lie ahead if these trends continue.
Proceedings ArticleDOI
DIVA: a reliable substrate for deep submicron microarchitecture design
TL;DR: It is argued that the DIVA checker should lend itself to functional and electrical verification better than a complex core processor, and overall design cost can be dramatically reduced because designers need only verify the correctness of the checker unit.
Journal ArticleDOI
Intrinsic MOSFET parameter fluctuations due to random dopant placement
TL;DR: These fluctuations are shown to pose severe barriers to the scaling of supply voltage and channel length and thus, to the minimization of power dissipation and switching delay in multibillion transistor chips of the future, and can be reduced to some degree by selecting optimal values of channel width.