Proceedings ArticleDOI
Performance and Variability Optimization Strategies in a Sub-200mV, 3.5pJ/inst, 11nW Subthreshold Processor
Scott Hanson,Bo Zhai,Mingoo Seok,Brian Cline,K. Zhou,M. Singhal,M. Minuth,J. Olson,Leyla Nazhandali,Todd Austin,Dennis Sylvester,David Blaauw +11 more
- pp 152-153
TLDR
A robust, energy efficient subthreshold (sub-V<sub>th</sub>) processor has been designed and tested in a 0.13 mum technology and Variability and performance optimization techniques are investigated for sub-V</sub> circuits.Abstract:
A robust, energy efficient subthreshold (sub-Vth) processor has been designed and tested in a 0.13 mum technology. The processor consumes 11 nW at Vdd = 160 mV and 3.5 pJ/inst at Vdd = 350 mV. Variability and performance optimization techniques are investigated for sub-Vth circuits.read more
Citations
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Journal ArticleDOI
Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits
TL;DR: In this paper, the authors define and explore near-threshold computing (NTC), a design space where the supply voltage is approximately equal to the threshold voltage of the transistors.
Near-Threshold Computing: Reclaiming Moore's Law Through Energy Efficient Integrated Circuits Future computer systems promise to achieve an energy reduction of 100 or more times with memory design, device structure, device fabrication techniques, and clocking, all optimized for low-voltage operation.
TL;DR: The barriers to the widespread adoption of near-threshold computing are explored and current work aimed at overcoming these obstacles are described.
Journal ArticleDOI
A 65 nm Sub- $V_{t}$ Microcontroller With Integrated SRAM and Switched Capacitor DC-DC Converter
TL;DR: A 65 nm system-on-a-chip which demonstrates techniques to mitigate variation, enabling sub-threshold operation down to 300 mV, and a switched capacitor DC-DC converter is integrated on-chip, achieving above 75% efficiency.
Proceedings ArticleDOI
0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS
Yasuyuki Okuma,Koichi Ishida,Yoshikatsu Ryu,Xin Zhang,Po-Hung Chen,Kazunori Watanabe,Makoto Takamiya,Takayasu Sakurai +7 more
TL;DR: The developed digital LDO in 65nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage are the lowest values in the published LDO's, which indicates the good energy efficiency of thedigital LDO at 0.
Journal ArticleDOI
A Subthreshold to Above-Threshold Level Shifter Comprising a Wilson Current Mirror
Sven Lütkemeier,Ulrich Rückert +1 more
TL;DR: A novel level shifter circuit that is capable of converting subthreshold to above-threshold signal levels and does not require a static current flow and can therefore offer considerable static power savings is proposed.
References
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TL;DR: In this article, the authors presented a study program to advance the state of the art in UHF limiters, octave-band ferrite circulators, and low-noise receivers having linear phase response suitable for pulse-compression applications.