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Radiation-induced SET on Flash-based FPGAs: Analysis and Filtering methods
Luca Sterpone,Sarah Azimi +1 more
- Vol. 1, pp 3-8
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TLDR
A new analysis to characterize the SET phenomena within Flashbased FPGAs and a new mitigation strategy based on the modification of the place and routed design to improve the filtering capability selectively adding electrical resistive capacitive loads without introducing performance degradation and introducing a limited overhead in terms of routing segments are proposed.Abstract:
Reliability of Integrated Circuits (ICs) it is nowadays a major concern for deep sub-micron technology. The progressive decreasing of device feature sizes provokes an increasing sensitiveness to radiation-induced particle strikes within the device silicon structure generating a larger number of Single Event Transients (SETs). In the present paper, we propose a new analysis to characterize the SET phenomena within Flashbased FPGAs. Besides, we developed a new mitigation strategy based on the modification of the place and routed design to improve the filtering capability selectively adding electrical resistive capacitive loads without introducing performance degradation and introducing a limited overhead in terms of routing segments. Experimental results performed on a various set of benchmark circuits shows a mitigation of SET improved of 3 orders of magnitude with respect to traditional logical filtering solutions with a minimal performance degradation of about 9%.read more
Citations
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Journal ArticleDOI
A new CAD tool for Single Event Transient Analysis and mitigation on Flash-based FPGAs
TL;DR: In this article, a CAD tool is presented for evaluating the sensitivity of the implemented circuit regarding SET and mitigating this effect, which has been applied to EUCLID space mission project including more than ten modules.
Journal ArticleDOI
Radiation-induced Single Event Transient effects during the reconfiguration process of SRAM-based FPGAs
TL;DR: An evaluation methodology for the errors caused by SETs during the reconfiguration of the configuration memory in SRAM-based FPGAs is presented and the obtained results are reported.
Proceedings ArticleDOI
A New Single Event Transient Hardened Floating Gate Configurable Logic Circuit
TL;DR: This paper evaluates the SET sensitivity of state-of-the-art floating gate configurable logic circuit and proposes a novel methodology for filtering a SET pulse generated inside the logic cells by increasing the charge sharing effect on the sensitive node of a cell due to remapping of its configurable switches.