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Reverse Engineering Intel DRAM Addressing and Exploitation

TLDR
This paper presents an automatic and generic method to reverse engineer DRAM addressing functions merely from performing a timing attack, and demonstrates the power of such attacks by implementing a high speed covert channel that achieves transmission rates of up to 1.5 Mb/s, three orders of magnitude faster than current covert channels on main memory.
Abstract
In this paper, we present a method to reverse engineer DRAM addressing functions based on a physical bus probing. Second, we present an automatic and generic method to reverse engineer DRAM addressing functions merely from performing a timing attack. This timing attack can be performed on any system without privileges and even in virtual machines to derive information about the mapping to physical DRAM channels, ranks and banks. We reversed the complex adressing functions on a diverse set of Intel processors and DRAM configurations. Our work enables side-channel attacks and covert channels based on inner-bank row conflicts and overlaps. Thus, our attack does not exploit the CPU as a shared resource, but only the DRAM that might even be shared across multiple CPUs. We demonstrate the power of such attacks by implementing a high speed covert channel that achieves transmission rates of up to 1.5 Mb/s, which is three orders of magnitude faster than current covert channels on main memory. Finally, we show how our results can be used to increase the efficiency of the Rowhammer attack significantly by reducing the search space by a factor of up to 16384.

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Posted Content

Intel SGX Explained.

TL;DR: In this article, the authors present a detailed and structured presentation of the publicly available information on SGX, a series of intelligent guesses about some important but undocumented aspects of SGX.
Book ChapterDOI

Rowhammer.js: A Remote Software-Induced Fault Attack in JavaScript

TL;DR: This work shows that caches can be forced into fast cache eviction to trigger the Rowhammer bug with only regular memory accesses, and demonstrates a fully automated attack that requires nothing but a website with JavaScript to trigger faults on remote hardware.
Proceedings ArticleDOI

Prefetch Side-Channel Attacks: Bypassing SMAP and Kernel ASLR

TL;DR: This work introduces Prefetch Side-Channel Attacks, a new class of generic attacks exploiting major weaknesses in prefetch instructions that allows unprivileged attackers to obtain address information and thus compromise the entire system by defeating SMAP, SMEP, and kernel ASLR.
Journal ArticleDOI

CacheBleed: a timing attack on OpenSSL constant-time RSA

TL;DR: A cache timing attack against the scatter-gather implementation used in the modular exponentiation routine in OpenSSL version 1.0.2f, which can fully recover the private key after observing 16,000 decryptions.
Book ChapterDOI

Curious Case of Rowhammer: Flipping Secret Exponent Bits Using Timing Analysis

TL;DR: An intelligent combination of timing Prime + Probe attack and row-buffer collision is shown to induce bit flip faults in a 1024 bit RSA key on modern processors using realistic number of hammering attempts, demonstrating the feasibility of fault analysis of ciphers using purely software means on commercial x86 architectures.
References
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Proceedings ArticleDOI

Hey, you, get off of my cloud: exploring information leakage in third-party compute clouds

TL;DR: It is shown that it is possible to map the internal cloud infrastructure, identify where a particular target VM is likely to reside, and then instantiate new VMs until one is placed co-resident with the target, and how such placement can then be used to mount cross-VM side-channel attacks to extract information from a target VM on the same machine.
Proceedings Article

FLUSH+RELOAD: a high resolution, low noise, L3 cache side-channel attack

TL;DR: This paper presents FLUSH+RELOAD, a cache side-channel attack technique that exploits a weakness in the Intel X86 processors to monitor access to memory lines in shared pages and recovers 96.7% of the bits of the secret key by observing a single signature or decryption round.
Journal ArticleDOI

Flipping bits in memory without accessing them: an experimental study of DRAM disturbance errors

TL;DR: This paper exposes the vulnerability of commodity DRAM chips to disturbance errors, and shows that it is possible to corrupt data in nearby addresses by reading from the same address in DRAM by activating the same row inDRAM.
Proceedings ArticleDOI

Last-Level Cache Side-Channel Attacks are Practical

TL;DR: This work presents an effective implementation of the Prime+Probe side-channel attack against the last-level cache of GnuPG, and achieves a high attack resolution without relying on weaknesses in the OS or virtual machine monitor or on sharing memory between attacker and victim.
Proceedings ArticleDOI

Cross-VM side channels and their use to extract private keys

TL;DR: This paper details the construction of an access-driven side-channel attack by which a malicious virtual machine (VM) extracts fine-grained information from a victim VM running on the same physical computer and demonstrates the attack in a lab setting by extracting an ElGamal decryption key from a victims using the most recent version of the libgcrypt cryptographic library.
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