Proceedings ArticleDOI
Router Buffer Caching for Managing Shared Cache Blocks in Tiled Multi-Core Processors
Joe Augustine,Raghavendra K,John Jose,Madhu Mutyam +3 more
- pp 239-246
TLDR
Wang et al. as mentioned in this paper proposed a congestion management technique in the LLC that equips the NoC router with small storage to keep a copy of heavily shared cache blocks, and also propose a prediction classifier in LLC controller.Citations
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Journal ArticleDOI
NCDE: In-Network Caching for Directory Entries to Expedite Data Access in Tiled-Chip Multiprocessors
TL;DR: In this paper , the authors explore the opportunity of mitigating problems associated with shared data access via in-network caching for directory entries (NCDE), which can utilize every input port's virtual channels to hold directory entries.
Journal ArticleDOI
NCDE: In-Network Caching for Directory Entries to Expedite Data Access in Tiled-Chip Multiprocessors
TL;DR: In this paper , the authors explore the opportunity of mitigating problems associated with shared data access via in-network caching for directory entries (NCDE), which can utilize every input port's virtual channels to hold directory entries.
References
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Spider: a high-speed network interconnect
TL;DR: SGI's Spider chip-Scalable, Pipelined Interconnect for Distributed Endpoint Routing-create a scalable, short-range network delivering hundreds of gigabytes per second in bandwidth to large configurations.
Book ChapterDOI
SPEComp: A New Benchmark Suite for Measuring Parallel Computer Performance
TL;DR: An overview of a new benchmark suite for parallel computers, SPEComp, which targets mid-size parallel servers and includes a number of science/engineering and data processing applications, is presented.
Proceedings ArticleDOI
Cache system design in the tightly coupled multiprocessor system
TL;DR: System requirements in the multiprocessor environment as well as the cost-performance trade-offs of the cache system design are given in detail and the possibility of sharing the Cache system hardware with other multiprocessioning facilities (such as dynamic address translation, storage protection, locks, serialization, and the system clocks) is discussed.
Proceedings ArticleDOI
In-Network Cache Coherence
TL;DR: This paper proposes an implementation of the cache coherence protocol within the network, embedding directories within each router node that manage and steer requests towards nearby data copies, enabling in-transit optimization of memory access delay.
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