Book ChapterDOI
ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors
Mohammad Hammoud,Sangyeun Cho,Rami Melhem +2 more
- pp 355-372
Reads0
Chats0
TLDR
Simulation results using a full system simulator demonstrate that the proposed controlled migration scheme outperforms the shared caching strategy and compares favorably with previously proposed replication schemes.Citations
More filters
Proceedings ArticleDOI
CloudCache: Expanding and shrinking private caches
TL;DR: This work proposes a novel scalable cache management framework called CloudCache that creates dynamically expanding and shrinking L2 caches for working threads with fine-grained hardware monitoring and control and demonstrates that CloudCache significantly improves performance of a wide range of workloads when all or a subset of cores are occupied.
Proceedings ArticleDOI
HK-NUCA: Boosting Data Searches in Dynamic Non-Uniform Cache Architectures for Chip Multiprocessors
TL;DR: A novel and implementable data search algorithm for D-NUCA designs in CMP architectures, called HK-N UCA (Home Knows where to find data within the NUCA cache), which exploits migration features by providing fast and power efficient accesses to data which is located close to the requesting core.
Patent
Accelerating cache state transfer on a directory-based multicore architecture
TL;DR: In this paper, the authors describe techniques for accelerating cache state transfer in a multicore processor, which includes first, second, and third tiles, and include a directory at the third tile corresponding to the block addresses.
Journal ArticleDOI
Exploiting replication to improve performances of NUCA-based CMP systems
TL;DR: Results show that a Re-NUCA LLC permits to improve performances of more than 5% on average, and up to 15% for applications that strongly suffer from conflicting access to shared data, while reducing network traffic and power consumption with respect to D-N UCA caches.
Proceedings ArticleDOI
The auction: optimizing banks usage in Non-Uniform Cache Architectures
TL;DR: A novel mechanism based on the bank replacement policy for NUCA caches on CMP, called The Auction, which manages the cache efficiently and significantly reduces the requests to the off-chip memory by increasing the hit ratio in the NU CA cache.
References
More filters
Proceedings ArticleDOI
The SPLASH-2 programs: characterization and methodological considerations
TL;DR: This paper quantitatively characterize the SPLASH-2 programs in terms of fundamental properties and architectural interactions that are important to understand them well, including the computational load balance, communication to computation ratio and traffic needs, important working set sizes, and issues related to spatial locality.
Proceedings ArticleDOI
An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches
TL;DR: This paper proposes physical designs for these Non-Uniform Cache Architectures (NUCAs) and extends these physical designs with logical policies that allow important data to migrate toward the processor within the same level of the cache.
Proceedings ArticleDOI
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS
Sriram R. Vangal,Jason Howard,G. Ruhl,Saurabh Dighe,H. Wilson,J. Tschanz,D. Finan,P. Iyer,A. Singh,Tiju Jacob,Shailendra Jain,S. Venkataraman,Y. Hoskote,Nitin Borkar +13 more
TL;DR: A 275mm2 network-on-chip architecture contains 80 tiles arranged as a 10 times 8 2D array of floating-point cores and packet-switched routers, operating at 4GHz, designed to achieve a peak performance of 1.0TFLOPS at 1V while dissipating 98W.
Journal ArticleDOI
Low-Latency Virtual-Channel Routers for On-Chip Networks
TL;DR: Simulations illustrate that dramatic cycle time improvements are possible without compromising router efficiency, and these reductions permit flits to be routed in a single cycle, maximising the effectiveness of the router's limited buffering resources.
Proceedings ArticleDOI
Managing Wire Delay in Large Chip-Multiprocessor Caches
Bradford M. Beckmann,Darien Wood +1 more
TL;DR: This paper develops L2 cache designs for CMPs that incorporate block migration, stride-based prefetching between L1 and L2 caches, and presents a hybrid design-combining all three techniques-that improves performance by an additional 2% to 19% overPrefetching alone.