Patent
Semiconductor device with CMOS-field-effect transistors having improved drain current characteristics
Yukihiro Kumagai,Hiroyuki Ohta,Fumio Ootsuka,Shuji Ikeda,Takahiro Onai,Hideo Miura,Katsuhiko Ichinose,Toshifumi Takeda +7 more
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TLDR
In this paper, the authors presented a semiconductor device including n-channel field effect transistors and p-channel FEM transistors, all of which have excellent drain current characteristics.Abstract:
The present invention provides a semiconductor device including n-channel field effect transistors and p-channel field effect transistors all of which have excellent drain current characteristics. In a semiconductor device including an n-channel field effect transistor 10 and a p-channel field effect transistor 30 , a stress control film 19 covering a gate electrode 15 of the n-channel field effect transistor 10 undergoes film stress mainly composed of tensile stress. A stress control film 39 covering a gate electrode 15 of the p-channel field effect transistor 30 undergoes film stress mainly caused by compression stress compared to the film 19 of the n-channel field effect transistor 10 . Accordingly, drain current is expected to be improved in both the n-channel field effect transistor and the p-channel field effect transistor. Consequently, the characteristics can be generally improved.read more
Citations
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References
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Journal ArticleDOI
A new aspect of mechanical stress effects in scaled MOS devices
TL;DR: In this paper, a stress analysis program, SIMUS (stress analysis program for multilayer structure) 2D/F, which can analyze the stress state of thin multi-layer structures such as LSI devices throughout their manufacturing process, was used.
Patent
Semiconductor device and its manufacture
TL;DR: In this article, the authors proposed a method for manufacturing a high breakdown voltage transistor using low-concentration impurity diffusion layers as its source and drain and uniform electrical characteristics.
Patent
Method of fabricating a nitride capped MOSFET for integrated circuits
TL;DR: In this article, a method for fabricating a lightly doped drain MOSFET integrated circuit device is described, which is completed by forming a passivation layer over the structures described and appropriate electrical connecting structures thereover to electrically connect the gate electrode structures and source/drain elements.
Patent
Semiconductor device and manufacture thereof
Noriaki Oda,典明 小田 +1 more
TL;DR: In this article, the authors proposed a multi-layer wiring structure which can be optimized in its wiring capacity and resistance depending on circuit operational requests and wiring length, where the wires are connected to the corresponding lower wiring layers.
Patent
Method of fabricating gate electrode of CMOS device
Hyeon Soo Kim,Choong Hun Lee +1 more
TL;DR: In this article, a method of fabricating a gate electrode of a CMOS device is described, including the steps of: sequentially forming a gate insulating layer, first conductive layer and protective layer on a semiconductor substrate; selectively etching a predetermined portion of the protective layer in which a PMOS transistor will be formed; forming a second conductive surface on the overall surface of said substrate; removing the second conductives layer formed on the protection layer, and partially etching the protecting layer to a predetermined thickness.