Proceedings ArticleDOI
Shakti-T: A RISC-V Processor with Light Weight Security Extensions
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TLDR
This work presents a unified hardware framework for handling spatial and temporal memory attacks with a RISC-V based micro-architecture with an enhanced application binary interface that enables software layers to use these features to protect sensitive data.Abstract:
With increased usage of compute cores for sensitive applications, including e-commerce, there is a need to provide additional hardware support for securing information from memory based attacks. This work presents a unified hardware framework for handling spatial and temporal memory attacks. The paper integrates the proposed hardware framework with a RISC-V based micro-architecture with an enhanced application binary interface that enables software layers to use these features to protect sensitive data. We demonstrate the effectiveness of the proposed scheme through practical case studies in addition to taking the design through a VLSI CAD design flow. The proposed processor reduces the metadata storage overhead up to 4 x in comparison with the existing solutions, while incurring an area overhead of just 1914 LUTs and 2197 flip flops on an FPGA, without affecting the critical path delay of the processor.read more
Citations
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Proceedings ArticleDOI
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product
Chen Chen,Xiaoyan Xiang,Chang Liu,Yunhai Shang,Ren Guo,Dongqi Liu,Lu Yimin,Ziyi Hao,Jiahui Luo,Zhijian Chen,Chunqiang Li,Yu Pu,Jianyi Meng,Xiaolang Yan,Yuan Xie,Xiaoning Qi +15 more
TL;DR: Xuantie-910 is an industry leading 64-bit high performance embedded RISC-V processor from Alibaba T-Head division that features custom extensions to arithmetic operation, bit manipulation, load and store, TLB and cache operations, and implements the 0.7.1 stable release of RISCV vector extension specification for high efficiency vector processing.
Proceedings ArticleDOI
Lightweight Secure-Boot Architecture for RISC-V System-on-Chip
TL;DR: A lightweight hardware-based secure boot architecture that incorporates an optimized Physical Unclonable Function (PUF) for providing keys to the security blocks of the System on Chip (SoC), among which, secure boot and remote attestation are presented.
Proceedings ArticleDOI
SHAKTI-MS: a RISC-V processor for memory safety in C
TL;DR: The proposal is to use stack-based cookies for crafting fat-pointers instead of having object-based identifiers, which eliminates the use of shadow memory space, or any table to store the pointer metadata, and reduces the storage overheads by a great extent.
Journal ArticleDOI
Stack Redundancy to Thwart Return Oriented Programming in Embedded Systems
Cyril Bresch,David Hely,Athanasios Papadimitriou,Adrien Michelet-Gignoux,Laurent Amato,Thomas Meyer +5 more
TL;DR: A hardware-based countermeasure against return address corruption in the processor stack is proposed and validated on the OpenRISC core with a minimal hardware modification of the targeted core and an easy integration at the application level.
Journal ArticleDOI
Towards Designing a Secure RISC-V System-on-Chip: ITUS
Vinay B. Y. Kumar,Suman Deb,Naina Gupta,Shivam Bhasin,Jawad Haj-Yahya,Anupam Chattopadhyay,Avi Mendelson +6 more
TL;DR: This manuscript discusses a set of primitive building blocks of a secure SoC and presents some of the implemented security subsystems using these building blocks—such as secure boot, memory protection, PUF-based key management, a countermeasure methodology for RISC-V micro-architectural side-channel leakage, and an integration of the open keystone-enclaves for TEE.
References
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Proceedings ArticleDOI
Raksha: a flexible information flow architecture for software security
TL;DR: Raksha is proposed, an architecture for software security based on dynamic information flow tracking (DIFT) that supports flexible and programmable security policies that enable software to direct hardware analysis towards a wide range of high-level and low-level attacks.
Proceedings ArticleDOI
ROPdefender: a detection tool to defend against return-oriented programming attacks
TL;DR: This paper presents a tool, ROPdefender, that dynamically detects conventional ROP attacks (that are based on return instructions) and can be immediately deployed by end-users, since it does not rely on side information which is rarely provided in practice.
Proceedings Article
Baggy bounds checking: an efficient and backwards-compatible defense against out-of-bounds errors
TL;DR: A backwards compatible bounds checking technique that substantially reduces performance overhead and is more than two times faster than the fastest previous technique and about five times faster--using less memory--than recording object bounds using a splay tree.
Journal ArticleDOI
The CHERI capability model: revisiting RISC in an age of risk
Jonathan Woodruff,Robert N. M. Watson,David Chisnall,Simon W. Moore,Jonathan Anderson,Brooks Davis,Ben Laurie,Peter G. Neumann,Robert Norton,Michael Roe +9 more
TL;DR: CHERI, a hybrid capability model that extends the 64-bit MIPS ISA with byte-granularity memory protection, is presented, demonstrating that it enables language memory model enforcement and fault isolation in hardware rather than software, and that the CHERI mechanisms are easily adopted by existing programs for efficient in-program memory safety.
ReportDOI
The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0
TL;DR: RISC-V (pronounced risk-five) is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education, but which it is hoped will become a standard open architecture for industry implementations.