Single Event Upset: An Embedded Tutorial
Fan Wang,Vishwani D. Agrawal +1 more
- pp 429-434
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TLDR
A tutorial study of the radiation-induced single event upset phenomenon caused by external radiation, which is a major source of soft errors in silicon, is presented.Abstract:
With the continuous downscaling of CMOS technologies, the reliability has become a major bottleneck in the evolution of the next generation systems. Technology trends such as transistor down-sizing, use of new materials, and system on chip architectures continue to increase the sensitivity of systems to soft errors. These errors are random and not related to permanent hardware faults. Their causes may be internal (e.g., interconnect coupling) or external (e.g., cosmic radiation). To meet the system reliability requirements it is necessary for both the circuit designers and test engineers to get the basic knowledge of the soft errors. We present a tutorial study of the radiation-induced single event upset phenomenon caused by external radiation, which is a major source of soft errors. We summarize basic radiation mechanisms and the resulting soft errors in silicon. Soft error mitigation techniques with time and space redundancy are illustrated. An industrial design example, the IBM z990 system, shows how the industry is dealing with soft errors these days.read more
Citations
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Soft Errors in Modern Electronic Systems
TL;DR: In this article, the authors provide a comprehensive presentation of the most advanced research results and technological developments enabling understanding, qualifying and mitigating the soft errors effect in advanced electronics, including the fundamental physical mechanisms of radiation induced soft errors, the various steps that lead to a system failure, the modelling and simulation of soft error at various levels (including physical, electrical, netlist, event driven, RTL, and system level modeling and simulation), hardware fault injection, accelerated radiation testing and natural environment testing, soft error oriented test structures, process-level, device level, celllevel, circuit
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Multi Fault Laser Attacks on Protected CRT-RSA
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Modeling of Single Event Transients With Dual Double-Exponential Current Sources: Implications for Logic Cell Characterization
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Fault Model Analysis of Laser-Induced Faults in SRAM Memory Cells
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References
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