Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC
Donghyun Kim,Kwanho Kim,Joo-Young Kim,Seungjin Lee,Hoi-Jim Yoo +4 more
- pp 30-39
TLDR
This paper proposes memory centric NoC (MC-NoC) for homogeneous multi processor SoC (MPSoC) and Experimental result obtained by mapping edge detection tasks on the MC- noC in various configurations shows almost constant performance, which proves the effectiveness of the proposed architecture.Abstract:
This paper describes real chip implementation issues of network-on-chip (NoC) and their solutions along with series of chip design examples. The solutions described in this paper cover both architectural aspects and circuit level techniques for practical chip implementation of NoC. As for architecture level solutions, topology selection, chip-aware protocol design, and on-chip serialization (OCS) for link area reduction are explained. For circuit level techniques, SERDES and synchronizer design, crossbar switch partial activation, and low-voltage link are presented as the foundations for power and area efficient NoC implementation. Regarding presented solutions for NoC implementation, this paper proposes memory centric NoC (MC-NoC) for homogeneous multi processor SoC (MPSoC). Flexibility and feasibility of task mapping on homogeneous SoC is the key feature of the MC-NoC. 8 dual port SRAMs connected to crossbar switches in hierarchical star topology network facilitate data communication between processors, regardless of task mapping into the MC-NoC. Experimental result obtained by mapping edge detection tasks on the MC-NoC in various configurations shows almost constant performance. This result proves the effectiveness of the proposed architecture. The MC-NoC based SoC is also implemented on TSMC 0.18 um process technologyread more
Citations
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Journal ArticleDOI
Outstanding Research Problems in NoC Design: System, Microarchitecture, and Circuit Perspectives
TL;DR: This paper provides a general description of NoC architectures and applications and enumerates several related research problems organized under five main categories: Application characterization, communication paradigm, communication infrastructure, analysis, and solution evaluation.
Proceedings ArticleDOI
A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters
TL;DR: A parametric, fully combinational Mesh-of-Trees (MoT) interconnection network to support high-performance, single-cycle communication between processors and memories in L1-coupled processor clusters is designed.
Journal ArticleDOI
The Chip Is the Network: Toward a Science of Network-on-Chip Design
Radu Marculescu,Paul Bogdan +1 more
TL;DR: This survey addresses the concept of network in three different contexts representing the deterministic, probabilistic, and statistical physics-inspired design paradigms by considering the natural representation of networks as graphs.
Proceedings ArticleDOI
Homogeneous NoC-based FPGA: The Foundation for Virtual FPGA
TL;DR: A homogeneous NoC-based FPGA architecture is proposed, in which reconfigurable and I/O resources are interconnected via NoC so that reconfigured modules can be placed anywhere once enough space available.
Proceedings ArticleDOI
Network Interface Sharing Techniques for Area Optimized NoC Architectures
TL;DR: While area improvements are significant, a number of physical and system-level effects might mitigate performance degradation, making the technique a promising solution for area efficient network-on-chip realizations across a range of operating conditions.
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