Journal ArticleDOI
Statistical Fault Analysis
TLDR
Among Stafan's advantages, fault coverage and the undetected fault data obtained for actual circuits are shown to agree within five percent of fault simulator results, yet CPU time and memory demands fall far short of those required in fault simulation.Abstract:
Statistical Fault Analysis, or Stafan, is proposed as an alternative to fault simulation of digital circuits. This method defines Controllabilities and observabilities of circuit nodes as probabilities estimated from signal statistics of fault-free simulation. Special Procedures deal with these quantities at fanout and feedback nodes. The computed probabilities are used to derive unbiased estimates of fault detection probabilities and overall fault coverage for the given set of input vectors. Among Stafan's advantages, fault coverage and the undetected fault data obtained for actual circuits are shown to agree within five percent of fault simulator results, yet CPU time and memory demands fall far short of those required in fault simulation. The Computational complexity added to a fault-free simulator by Stafan grows only linearly with the number of circuit nodes.read more
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VLSI Test Principles and Architectures: Design for Testability
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Proceedings ArticleDOI
Estimate of signal probability in combinational logic networks
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Constructive multi-phase test point insertion for scan-based BIST
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TL;DR: Experimental results demonstrate that complete or near-complete stuck-at fault coverage can be achieved by the proposed technique with the insertion of a few test points and a minimum number of phases.
References
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Journal ArticleDOI
Controllability/observability analysis of digital circuits
TL;DR: The testability of a digital circuit is directly related to the difficulty of controlling and observing the logical values of internal nodes from circuit inputs and outputs, respectively as mentioned in this paper, and the testability is also related to how well the internal nodes can be controlled and observed.
Controllability/observability analysis of digital circuits
TL;DR: The testability of a digital circuit is directly related to the difficulty of controlling and observing the logical values of internal nodes from circuit inputs and outputs, respectively as discussed by the authors, and the testability is also related to how well the internal nodes can be controlled and observed.
Journal ArticleDOI
Random Pattern Testability
TL;DR: A new analytical method of computing the fault coverage that is fast compared with simulation is described that is possible to identify the ``random-pattern-resistant'' faults, modify the logic to make them easy to detect, and thus, increase the fault Coverage of the random test.
Journal ArticleDOI
Critical Path Tracing: An Alternative to Fault Simulation
TL;DR: Critical path tracing determines fault detection without explicit fault simulation, and appears to be a more efficient alternative to conventional methods.
Proceedings ArticleDOI
Critical Path Tracing - An Alternative to Fault Simulation
TL;DR: This work presents an alternative to fault simulation, referred to as critical path tracing, that determines the faults detected by a set of tests using a backtracing algorithm starting at the primary outputs of a circuit.