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Super Pipelined Digit Serial Adders for Multimedia and e-Security

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TLDR
This paper presents super-pipelined models of conventional adders that use digit serial addition, and pipeline three adders: ripple carry, carry select, and carry lookahead showing the pipelining effect in their speed and area.
Abstract
This paper presents super-pipelined models of conventional adders that use digit serial addition. We pipeline three adders: ripple carry, carry select, and carry lookahead showing the pipelining effect in their speed and area. An improvement to the pipelined carry lookahead adder is proposed showing interesting results.

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References
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Journal ArticleDOI

A Regular Layout for Parallel Adders

TL;DR: It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.
Journal ArticleDOI

Area-time-power tradeoffs in parallel adders

TL;DR: A uniform static CMOS layout methodology whereby short circuit power mininization is used as the optimization criterion is adopted and a large adder design space is formulated from which an architect can choose an adder with the desired characteristics.
Proceedings ArticleDOI

Hardware implementation

TL;DR: The area of hardware implementation shall be (some-what arbitrarily) defined to include placement, wire routing, terminal assignment, and the interface to hardware fabrication devices.
Journal ArticleDOI

Self-timed carry-lookahead adders

TL;DR: In this article, the authors proposed a self-timed carry-lookahead adder in which the logic complexity is a linear function of n, the number of inputs, and the average computation time is proportional to the logarithm of the log of n. This adder has the best area-time efficiency which is /spl Theta/(nloglogn).
Journal ArticleDOI

Pipelined adders

TL;DR: This paper shows that other schemes can be designed, based on the idea of pipelining a serial-input adder or a ripple-carry adder, to obtain pipelined adders for more than two numbers.