Open AccessDOI
Synthesis of On-Chip Interconnection Structures: From Point-To-Point Links to Networks-on-Chip
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This work presents a novel approach to on-chip communication synthesis that is based on the iterative combination of two efficient computational steps: an application of the k-Median algorithm to coarsely determine the global communication structure and a variation of the shortest-path algorithm in order to finely tune the data flows on the communication channels.Abstract:
Packet-switched networks-on-chip (NOC) have been advocated as the solution to the challenge of organizing efficient and reliable communication structures among the components of a system-on-chip (SOC). A critical issue in designing a NOC is to determine its topology given the set of point-to-point communication requirements among these components. We present a novel approach to on-chip communication synthesis that is based on the iterative combination of two efficient computational steps: (1) an application of the k-Median algorithm to coarsely determine the global communication structure (which may turned out not be a network after all), and a (2) a variation of the shortest-path algorithm in order to finely tune the data flows on the communication channels. The application of our method to case studies taken from the literature shows that we can automatically synthesize optimal NOC topologies for multi-core on-chip processors and it offers new insights on why NOC are not necessarily a value proposition for some classes of application-specific SOCs.read more
Citations
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Proceedings ArticleDOI
NoCOUT: NoC topology generation with mixed packet-switched and point-to-point networks
Jeremy Chan,Sri Parameswaran +1 more
TL;DR: NoCOUT is presented, a methodology for generating an energy optimized application specific NoC topology which supports both point-to-point and packet-switched networks and achieves approximately 25% lower energy consumption than a state of the art min-cut partition based topology generator for a variety of benchmarks.
Proceedings ArticleDOI
Efficient Congestion-Oriented Custom Network-on-Chip Topology Synthesis
TL;DR: Experimental results demonstrate that custom irregular NoC topologies can achieve latencies comparable to those achieved by 2-layer 3D regular mesh topologies.
References
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Approximation Algorithms
TL;DR: Covering the basic techniques used in the latest research work, the author consolidates progress made so far, including some very recent and promising results, and conveys the beauty and excitement of work in the field.
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Luca Benini,G. De Micheli +1 more
TL;DR: Focusing on using probabilistic metrics such as average values or variance to quantify design objectives such as performance and power will lead to a major change in SoC design methodologies.
Proceedings ArticleDOI
Route packets, not wires: on-chip interconnection networks
William J. Dally,Brian Towles +1 more
TL;DR: This paper introduces the concept of on-chip networks, sketches a simple network, and discusses some challenges in the architecture and design of these networks.
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Low-Power CMOS Digital Design
TL;DR: An architecturally based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations, and is achieved by trading increased silicon area for reduced power consumption.
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