Journal ArticleDOI
Techniques for Random Masking in Hardware
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TLDR
A new technique for Boolean random masking of the logic and operation in terms of nand logic gates is proposed and applied for masking the integer addition and is more efficient than previously known techniques.Abstract:
A new technique for Boolean random masking of the logic and operation in terms of nand logic gates is proposed and applied for masking the integer addition. The new technique can be used for masking arbitrary cryptographic functions and is more efficient than previously known techniques, recently applied to the Advanced Encryption Standard (AES). New techniques for the conversions from Boolean to arithmetic random masking and vice versa are also developed. They are hardware oriented and do not require additional random bits. Unlike the previous, software-oriented techniques showing a substantial difference in the complexity of the two conversions, they have a comparable complexity being about the same as that of one integer addition only. All the techniques proposed are in theory secure against the first-order differential power analysis on the logic gate level. They can be applied in hardware implementations of various cryptographic functions, including AES, (keyed) SHA-1, IDEA, and RC6read more
Citations
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Journal ArticleDOI
FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network
TL;DR: This brief aims to optimize the area for a masked AES with an unrolled structure by reducing the number of mapping and inverse mapping operations of the masked SubBytes step from ten to one and using FPGA block RAM (BRAM) to further reduce hardware resources.
Journal ArticleDOI
Lightweight Hardware Architectures for the Present Cipher in FPGA
TL;DR: The hardware implementations of Present, a standardized lightweight cipher called to overcome part of the security issues in extremely constrained environments, are discussed and the most representative realizations of this cipher are reviewed and two novel designs are presented.
Book ChapterDOI
Differential power analysis of HMAC based on SHA-2, and countermeasures
TL;DR: This paper describes a DPA attack strategy for the HMAC algorithm, based on the SHA-2 hash function family, and presents a masked implementation of the algorithm, which is designed to counteract first-order DPA attacks.
Book ChapterDOI
Arithmetic Addition over Boolean Masking
TL;DR: In this paper, the authors present a hardware design that fulfills relevant properties such as efficiency and security at the same time, but to the best of their knowledge, no hardware design exists that fulfils relevant properties for side-channel analysis attacks.
Proceedings ArticleDOI
FPGA based optimization for masked AES implementation
TL;DR: The experimental results show that the proposed masked AES encryption with 32-bit and 128-bit data path hardware implementation takes up less hardware resources and has the ability to defend against differential power analysis (DPA) and glitch attacks.
References
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Book ChapterDOI
Differential Power Analysis
TL;DR: In this paper, the authors examine specific methods for analyzing power consumption measurements to find secret keys from tamper resistant devices. And they also discuss approaches for building cryptosystems that can operate securely in existing hardware that leaks information.
Book
The Design of Rijndael: AES - The Advanced Encryption Standard
Joan Daemen,Vincent Rijmen +1 more
TL;DR: The underlying mathematics and the wide trail strategy as the basic design idea are explained in detail and the basics of differential and linear cryptanalysis are reworked.
Book ChapterDOI
Towards Sound Approaches to Counteract Power-Analysis Attacks
TL;DR: An abstract model which approximates power consumption in most devices and in particular small single-chip devices is proposed, and a lower bound on the number of experiments required to mount statistical attacks on devices whose physical characteristics satisfy reasonable properties is proved.
Book ChapterDOI
Private Circuits: Securing Hardware against Probing Attacks
TL;DR: This paper proposes several efficient techniques for building private circuits resisting side channel attacks, and provides a formal threat model and proofs of security for their constructions.
Book ChapterDOI
A proposal for a new block encryption standard
Xuejia Lai,James L. Massey +1 more
TL;DR: A new secret-key block cipher is proposed as a candidate for a new encryption standard, based on the design concept of mixing operations from different algebraic groups.