Proceedings ArticleDOI
Test pattern generation for signal integrity faults on long interconnects
A. Attarha,Mehrdad Nourani +1 more
- pp 336-341
TLDR
A test pattern generation algorithm aiming at signal integrity faults on long interconnects is presented by considering the effect of inputs and parasitic RLC elements of the interconnect by model order reduction methodology.Abstract:
In this paper we present a test pattern generation algorithm aiming at signal integrity faults on long interconnects. This is achieved by considering the effect of inputs and parasitic RLC elements of the interconnect. To enhance the performance of test generation process, model order reduction methodology is employed. This strategy significantly improves the simulation time with slight loss of accuracy.read more
Citations
More filters
Book
VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)
TL;DR: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time- to-volume.
Book
VLSI Test Principles and Architectures: Design for Testability
TL;DR: A comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time to market and time-to-volume as mentioned in this paper.
Book
System-on-Chip Test Architectures: Nanometer Design for Testability
TL;DR: This book is a comprehensive guide to new VLSI Testing and Design-for-Testability techniques that will allow students, researchers, DFT practitioners, and V LSI designers to master quickly System-on-Chip Test architectures, for test debug and diagnosis of digital, memory, and analog/mixed-signal designs.
Proceedings ArticleDOI
Testing SoC interconnects for signal integrity using boundary scan
TL;DR: This paper extends the conventional boundary scan architecture to allow testing signal integrity in SoC interconnects and collects and outputs the integrity loss information using the enhanced observation cells, and proposes a simple yet efficient compression scheme that can be employed by an ATE to minimize the scan-in delivery time.
Journal ArticleDOI
Testing SoC interconnects for signal integrity using extended JTAG architecture
TL;DR: This paper proposes an enhanced boundary-scan architecture to test high-speed interconnects for signal integrity that includes a modified driving cell that generates patterns according to multiple transitions fault model and an observation cell that monitors signal integrity violations.
References
More filters
Book
Digital Systems Testing and Testable Design
TL;DR: The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Journal ArticleDOI
Asymptotic waveform evaluation for timing analysis
L.T. Pillage,R.A. Rohrer +1 more
TL;DR: Asymptotic waveform evaluation (AWE) provides a generalized approach to linear RLC circuit response approximations and reduces to the RC tree methods.
Journal ArticleDOI
The Transient Response of Damped Linear Networks with Particular Regard to Wideband Amplifiers
TL;DR: It is found possible to define delay time and rise time in such a way that these quantities can be computed very simply from the Laplace system function of the network.
Book
Digital Integrated Circuits
TL;DR: Digital Integrated Circuits as discussed by the authors is a practical book that bridges the gap between the circuit perspective and system perspective of digital integrated circuit design, including the impact of interconnect, design for low power, issues in timing and clocking, design methodologies and the tremendous effect of design automation on the digital design perspective.
Journal ArticleDOI
Efficient linear circuit analysis by Pade approximation via the Lanczos process
Peter Feldmann,Roland W. Freund +1 more
TL;DR: In this article, the Lanczos process is used to compute the Pade approximation of Laplace-domain transfer functions of large linear networks via a Lanczos Process (PVL) algorithm.