Journal ArticleDOI
The temperature dependence of threshold voltages in submicrometer CMOS
TLDR
In this article, the temperature coefficient of the threshold voltage in long buried-p-channel MOSFET is 2.02 mV/°C, which is much larger than that in the long enhancement-mode n-channel MCM.Abstract:
The temperature coefficient of the threshold voltage in long buried-p-channel MOSFET is dV_{th}/dT = 2.02 mV/°C, which is much larger than that in the long enhancement-mode n-channel MOSFET (-1.27 mV/°C). The difference is caused by the charge freeze-out phenomenon in the buried-channel MOSFET. The absolute value of the temperature coefficient of the threshold voltage |dV_{th}/dT| , decreases with decreasing channel length in the n-channel MOSFET, however, it increases with decreasing channel length in the submicrometer p-channel MOSFET. The difference results from the majority-carrier spill-over phenomenon in the buried-p-channel MOSFET.read more
Citations
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Journal ArticleDOI
On the temperature coefficient of the MOSFET threshold voltage
F.M. Klaassen,W. Hes +1 more
TL;DR: In this article, the temperature coefficient of the threshold voltage of the most common types of MOSFET devices has been measured and analyzed in terms of the underlying device physics, due to differences in gate contact potential and anomalies of the substrate backbias effect.
Proceedings ArticleDOI
On improving reliability of delay based Physically Unclonable Functions under temperature variations
TL;DR: Two methods for improving the reliability of delay based PUFs, by reducing temperature sensitivity and exploiting the negative temperature coefficient (TCR) property of n+ and p+ polysilicon placed as source feedback resistors are proposed.
Journal ArticleDOI
High-performance salicide shallow-junction CMOS devices for submicrometer VLSI application in twin-tub VI
TL;DR: In this paper, the HIPOX twin-tub structure, n/sup +/p/sup+/ dual-type poly gate, 125-AA thin gate oxide, shallow junctions, rapid thermal anneal activation, and thin TiSi/sub 2/ as the source/drain/gate silicide layer.
Journal ArticleDOI
CMOS reliability issues for emerging cryogenic Lunar electronics applications
Tianbing Chen,Tianbing Chen,Chendong Zhu,Laleh Najafizadeh,Bongim Jun,A. Ahmed,R.M. Diestelhorst,G. Espinel,John D. Cressler +8 more
TL;DR: In this paper, the authors investigate the reliability issues associated with the application of CMOS devices contained within an advanced SiGe HBT BiCMOS technology to emerging cryogenic space electronics (e.g., down to 43 K, for Lunar missions).
Proceedings ArticleDOI
On Design of Temperature Invariant Physically Unclonable Functions Based on Ring Oscillators
TL;DR: This paper exploits the negative temperature resistance property of n+ and p+ polysilicon placed as source feedback resistors to de-sensitize ring oscillators to temperature variations and proposes a temperature-invariant ring oscillator PUF architecture based on Serial-Input Serial-Output (SISO) topology.
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