Journal ArticleDOI
Ultralow-power adiabatic circuit semi-custom design
A. Blotti,Roberto Saletti +1 more
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This brief shows that a conventional semi-custom design-flow based on a positive feedback adiabatic logic (PFAL) cell library allows any VLSI designer to design and verify complex adiAbatic systems in a short time and easy way, thus, enjoying the energy reduction benefits of adiABatic logic.Abstract:
This brief shows that a conventional semi-custom design-flow based on a positive feedback adiabatic logic (PFAL) cell library allows any VLSI designer to design and verify complex adiabatic systems (e.g., arithmetic units) in a short time and easy way, thus, enjoying the energy reduction benefits of adiabatic logic. A family of semi-custom PFAL carry lookahead adders and parallel multipliers were designed in a 0.6-/spl mu/m CMOS technology and verified. Post-layout simulations show that semi-custom adiabatic arithmetic units can save energy a factor 17 at 10 MHz and about 7 at 100 MHz, as compared to a logically equivalent static CMOS implementation. The energy saving obtained is also better if compared to other custom adiabatic circuit realizations and maintains high values (3/spl divide/6) even when the losses in power-clock generation are considered.read more
Citations
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Journal ArticleDOI
Cascadable adiabatic logic circuits for low-power applications
TL;DR: A family of adiabatic circuits, which consist of two branches and which enable control of charging and discharging of the capacitive load only by the input signal, work with single time varying supply and with no need of complementary inputs are proposed.
Journal ArticleDOI
Low power adiabatic logic based on FinFETs
TL;DR: Due to the lower leakage current, higher on-state current and design flexibility of FinFETs, the proposed adiabatic logic shows considerable power reduction, performance improvement and area saving compared with CMOS adiABatic logic.
Posted Content
Secure Adiabatic Logic: a Low-Energy DPA-Resistant Logic Style.
Mehrdad Khatir,Amir Moradi +1 more
TL;DR: A new charge recovery logic style is presented not only to gain high energy efficiency but also to achieve the resistance against side-channel attacks (SDA) especially against differential power analysis (DPA) attacks.
Proceedings ArticleDOI
An efficient high speed Wallace tree multiplier
TL;DR: This paper aims at further reduction of the latency and power consumption of the Wallace tree multiplier by the use of 4:2, 5:2 compressors and a proposed carry select adder.
Journal ArticleDOI
DFAL: Diode-Free Adiabatic Logic Circuits
TL;DR: Low power high speed adiabatic circuit topology is proposed by removing the diode from the charging and discharging path, higher output amplitude is achieved and also the power dissipation of the diodes is eliminated, and the energy efficiency has been improved.
References
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Journal ArticleDOI
A Regular Layout for Parallel Adders
TL;DR: It is shown that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.
Journal ArticleDOI
Low-power digital systems based on adiabatic-switching principles
TL;DR: The dissipation of the adiabatic amplifier is compared to that of conventional switching circuits, both for the case of a fixed voltage swing and the case when the voltage swing can be scaled to reduce power dissipation.
Book
Low power CMOS VLSI circuit design
Kaushik Roy,Sharat Prasad +1 more
TL;DR: Low--Power CMOS VLSI Design and Test of Low--Voltage CMOS Circuits and Low--Energy Computing Using Energy Recovery Techniques.
Journal ArticleDOI
An efficient charge recovery logic circuit
Yong Moon,Deog-Kyoon Jeong +1 more
TL;DR: Efficient charge recovery logic (ECRL) is proposed as a candidate for low-energy adiabatic logic circuit and shows four to six times power reduction with a practical loading and operation frequency range.