Proceedings ArticleDOI
Wafer scale integration
David A. Patterson,S. Seccombe +1 more
- pp 124-125
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In this article, the authors discuss unique technological approaches and the future potentials along with limitations that may arise, and assess the problems that limited early implementations in the 60s and if they can be overcome; and if wafer scale integration will provide new opportunities such as systolic arrays, connection-oriented architectures and other related disciplines.Abstract:
With lowering defect densities in LSI fabrication technologies interest in wafer scale integration has revived. The process holds the promise of higher performance, lower cost, and increased packing density, particularly at the system level. However, it is necessary to consider if recent advances are sufficient to outweigh problems in testing, repairability and system configuration, ancl flexibility. To be assessed too are the problems that limited early implementations in the 60s and if they can be overcome; and if wafer scale integration will provide new opportunities such as systolic arrays, connection-oriented architectures and other related disciplines . . . Panelists will discuss unique technological approaches and the future potentials along with limitations that may arise.read more
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TL;DR: In this article, a wheel decorating ornament comprising an annular, planar sheet of material decorated on opposite sides, axially disposed between the groups of spokes and radially disposed at the rim and the hub, is presented.
Journal ArticleDOI
Fault tolerance in VLSI circuits
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TL;DR: Yield models for predicting the yield of chips with redundancy are introduced, and the optimal amount of redundancy is determined.
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Neural networks in analog hardware--design and implementation issues.
TL;DR: This paper presents a brief review of some analog hardware implementations of neural networks, including a unified review of various "VLSI friendly" algorithms.
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A mixed-signal implementation of a polychronous spiking neural network with delay adaptation.
TL;DR: A mixed-signal implementation of a re-configurable polychronous spiking neural network capable of storing and recalling spatio-temporal patterns and the experimental results are presented.
Book ChapterDOI
Laser Restructurable Technology and Design
TL;DR: The Restructurable VLSI project at MIT Lincoln Laboratory has developed a design methodology, new technology, and CAD tools for WSI and six wafer scale systems have been fabricated and three of much larger size are being designed.
References
More filters
Book
The Test Access Port and Boundary Scan Architecture
Colin Maunder,Rodham E. Tulloss +1 more
TL;DR: In this article, a wheel decorating ornament comprising an annular, planar sheet of material decorated on opposite sides, axially disposed between the groups of spokes and radially disposed at the rim and the hub, is presented.
Journal ArticleDOI
Fault tolerance in VLSI circuits
Israel Koren,A.D. Singh +1 more
TL;DR: Yield models for predicting the yield of chips with redundancy are introduced, and the optimal amount of redundancy is determined.
Journal ArticleDOI
Neural networks in analog hardware--design and implementation issues.
TL;DR: This paper presents a brief review of some analog hardware implementations of neural networks, including a unified review of various "VLSI friendly" algorithms.
Journal ArticleDOI
A mixed-signal implementation of a polychronous spiking neural network with delay adaptation.
TL;DR: A mixed-signal implementation of a re-configurable polychronous spiking neural network capable of storing and recalling spatio-temporal patterns and the experimental results are presented.
Book ChapterDOI
Laser Restructurable Technology and Design
TL;DR: The Restructurable VLSI project at MIT Lincoln Laboratory has developed a design methodology, new technology, and CAD tools for WSI and six wafer scale systems have been fabricated and three of much larger size are being designed.