Showing papers on "Asynchronous communication published in 1991"

An Object Calculus for Asynchronous Communication

Abstract: This paper presents a formal system based on the notion of objects and asynchronous communication Built on Milner's work on π-calculus, the communication primitive of the formal system is purely based on asynchronous communication, which makes it unique among various concurrency formalisms Computationally this results in a consistent reduction of Milner's calculus, while retaining the same expressive power Seen semantically asynchronous communication induces a surprisingly different framework where bisimulation is strictly more general than its synchronous counterpart This paper shows basic construction of the formal system along with several illustrative examples

Computer system which supports asynchronous commitment of data

Abstract: A computer system for processing and committing data comprises a processor, an external storage device such as DASD or tape coupled to the processor, and a working memory such as RAM. An application program updates data in the working memory and then requests that the data be committed, i.e. written to the external storage device. In response, an operating system function determines which data or blocks have been changed and supplies to an I/O service an identification of the changed data or blocks to cause the I/O service to write the changed data or blocks to the external storage device. Thus, the application program is not burdened with the management of the I/O. The operating system permits the program to continue with other processing while the data is being written from the working memory to the external storage device. As a result, the program need not wait while the data is written to the external storage. Also, because little time is required of the program in the commit process, the program can frequently request commits. With frequent commits, there is less chance that the data will have been written to back-up memory or back-up storage (due to an overload of the working memory) between commits, and as a result, time will not be required to read the data from the back-up memory or storage into the working memory en route to the application program's external storage. Also, the frequent commits reduce the chance of overloading the I/O subsystem.

Modeling and performance comparison of policing mechanisms for ATM networks

Abstract: Asynchronous transfer mode (ATM) networks, as proposed by CCITT as the solution for the future broadband ISDN, will provide high flexibility with respect to the varying bandwidth requirements of the different services. They will also support variable bit rates within a connection. The packetized information transfer, without flow control between the user and the network, in combination with the asynchronous multiplexing principle, results in a need to control the individual cell stream during the entire duration of the calls to ensure an acceptable quality of service for all coexisting calls sharing the same network resources. This kind of control will be provided by introducing a policing or usage parameter control function. Basic design objectives and requirements for such a function are described. These requirements serve as a basis for the comparison of some of the mechanisms proposed so far, namely the leaky bucket, the jumping window, the triggered jumping window, the moving window, and the exponentially weighted moving average mechanisms. >

Fault tolerant computer system

Abstract: A method and apparatus for providing a fault-tolerant backup system such that if there is a failure of a primary processing system, a replicated system can take over without interruption. The invention provides a software solution for providing a backup system. Two servers are provided, a primary and secondary server. The two servers are connected via a communications channel. The servers have associated with them an operating system. The present invention divides this operating system into two "engines." An I/O engine is responsible for handling and receiving all data and asynchronous events on the system. The I/O engine controls and interfaces with physical devices and device drivers. The operating system (OS) engine is used to operate on data received from the I/O engine. All events or data which can change the state of the operating system are channeled through the I/O engine and converted to a message format. The I/O engine on the two servers coordinate with each other and provide the same sequence of messages to the OS engines. The messages are provided to a message queue accessed by the OS engine. Therefore, regardless of the timing of the events, (i.e., asynchronous events), the OS engine receives all events sequentially through a continuous sequential stream of input data. As a result, the OS engine is a finite state automata with a one-dimensional input "view" of the rest of the system and the state of the OS engines on both primary and secondary servers will converge.

Performance comparison of asynchronous and synchronous code-division multiple-access techniques for fiber-optic local area networks

Abstract: Synchronous code-division multiple access (S/CDMA) is investigated for fiber-optic local area networks. It is shown that the large bandwidth expansion required by spread-spectrum techniques, such as CDMA, can be accommodated by using a fiber-optic channel for transmission and incoherent optical signal processing for code generation and correlation. Prime sequence codes, previously developed for a fiber-optic network using (asynchronous) CDMA, are modified to fit a synchronous transmission format. A performance comparison of CDMA and S/CDMA systems reveals that S/CDMA can accommodate a larger number of subscribers and more simultaneous users than CDMA. An environment for which S/CDMA would be suited is discussed. >

Replica control in distributed systems: as asynchronous approach

Abstract: An asynchronous approach is proposed for replica control in distributed systems. This approach applies an extension of serializability called epsilon-serializability (ES R), a correctness criterion which allows temporary and bounded inconsistency in replicas to be seen by queries. Moreover, users can reduce the degree of inconsistency to the desired amount. In the limit, users see strict l-copy serializability. Because the system maintains ESR correctness (1) replicas always converges to global serializability and (2) the system permits read access to object replicas before the system reaches a quiescent state. Various replica control methods that maintain ESR are described and analyzed. Because these methods do not require users to refer explicitly to ESR criteria, they can be easily encapsulated in high-level applications that use replicated data.

Distributed constrained heuristic search

Abstract: A model of decentralized problem solving, called distributed constrained heuristic search (DCHS), that provides both structure and focus in individual agent search spaces to optimize decisions in the global space, is presented. The model achieves this by integrating decentralized constraint satisfaction and heuristic search. It is a formalism suitable for describing a large set of distributed artificial intelligence problems. The notion of textures that allow agents to operate in an asynchronous concurrent manner is introduced. The use of textures coupled with distributed asynchronous backjumping, a type of distributed dependency-directed backtracking that the authors have developed, enables agents to instantiate variables in such a way as to substantially reduce backtracking. The approach has been tested experimentally in the domain of decentralized job-shop scheduling. A formulation of distributed job-shop scheduling as a DCHS and experimental results are presented. >

Performance Analysis and Optimization of Asynchronous Circuits

Abstract: Analytical techniques are developed to determine the performance of asynchronous digital circuits. These techniques can be used to guide the designer during the synthesis of such a circuit, leading to a high-performance, efficient implementation. Optimization techniques are also developed that further improve this implementation by determining the optimal sizes of the low-level devices (CMOS transistors) that compose the circuit. In order to determine the performance of an asynchronous circuit, it is first translated into an event-rule (ER) system, an abstract representation of the time dependencies (rules) between the primitive actions (events) of the circuit. This translation can be done from any of several different intermediate representations including: (i) a communicating sequential processes (CSP) program, (ii) a handshaking expansion, a refinement of the original CSP program in which all communication actions are replaced by explicit manipulations of boolean variables, (iii) a production rule set, a refinement of the handshaking expansion in which all sequencing is implemented by restricting concurrency, and (iv) a CMOS transistor network, a final representation from which the circuit can be fabricated. The analysis techniques are based on linear programming and provide an accurate approximation of the absolute time at which each event in an ER system occurs. Efficient algorithms for performing this approximation are developed and proven correct. Numerous examples are provided. This approximation can be represented as a formula expressing the performance of the circuit in terms of certain design variables, such as the widths of the transistors in the final CMOS network. This formula can be evaluated at particular width values and thus can be used to determine the performance of a particular realization of the circuit. Furthermore, using the techniques of convex programming, optimal transistor widths can be determined. The analysis techniques are applied to several large examples. Several implementations of first-in-first-out buffers are compared. A handshaking-expansion-level analysis of a simplified version of the Caltech Asynchronous Microprocessor is provided.

Using process groups to implement failure detection in asynchronous environments

Abstract: Agreement on the membership of a group of processes in a distributed system is a basic problem that arises in a wide range of applications. Such groups occur when a set of processes cooperate to perform some task, share memory, monitor one another, subdivide a computation, and so forth. The group membership problems is discussed as it relates to failure detection in asynchronous, distributed systems. A rigorous, formal specification for group membership is presented under this interpretation. A solution is then presented for this problem.

Synthesis of Asynchronous VLSI Circuits

Abstract: : With chip size reaching one million transistors. the complexity of VLSI algorithms-i.e., algorithms implemented as a digital VLSI circuit-is approaching that of software algorithms i.e., algorithms implemented as code for a stored-program computer. Yet design methods for VLSI algorithms lag far behind the potential of the technology. Since a digital circuit is the implementation of a concurrent algorithm, we propose a concurrent programming approach to digital VLSI design. The circuit to be designed is first implemented as a concurrent program that fulfills the logical specification of the circuit. The program is then compiled manually or automatically-into a circuit by applying semantic-preserving program transformations. Hence, the circuit obtained is correct by construction. The main obstacle to such a method is finding an interface that provides a good separation of the physical and algorithmic concerns. Among the physical parameters of the implementation, timing is the most difficult to isolate from the logical design, because the timing properties of a circuit are essential not only to its real time behavior but also to its logical correctness if the usual synchronous techniques are used to implement sequencing. For this reason, delay. insensitive' techniques are particularly attractive for VLSI synthesis. A circuit is delay-insensitive when its correct operation is independent of any assumption on delays in operators and wires except that the delays be finite. Such circuits do not use a clock signal or knowledge about delays. Let us clarify a matter of definitions right away: It has been proved in that the class of entirely delay-insensitive circuits is very limited. Different asynchronous techniques distinguish themselves in the choice of the compromises to delay-insensitivity.

Parallel synchronous and asynchronous implementations of the auction algorithm

Abstract: In this paper we discuss the parallel implementation of the auction algorithm for the classical assignment problem. We show that the algorithm admits a totally asynchronous implementation and we consider several implementations on a shared memory machine, with varying degrees of synchronization. We also discuss and explore computationally the tradeoffs involved in using asynchronism to reduce the synchronization penalty.

Computer‐mediated communication requirements for group support

Abstract: This paper talks about the requirements of computer-mediated communication (CMC) for group support. An overview of CMC's historical evolution is presented. Advantages of CMC include opportunity for group to exhibit "collective intelligence", asynchronous support of communication process, self-tailoring of communication structures by users and groups, and the integration into the communication system of other computer resources and information systems. The main advantage of using CMC is in the very fundamental nature of the communication medium. The asynchronous approaches to group problem solving free individuals to deal with problems in those cognitive processes at which they excel. Seven asynchronous group process factors are also presented. A CMC metaphor is also presented. The metaphor components discussed are conferences, messages, activities and notifications. A conference can be tailored according to activities. An activity can be attached to any communication item. When triggered, it will execute a program or procedure in the local or remote host. Notification functions include alerting, closure and tracking. The concepts of roles, privileges, and tickets are also discussed. Finally, the components of two CMC systems are presented. These components include an object-oriented database, distributed user and group agents, a master virtual machine, and a SGML interface specification language.

Algorithms for synthesis of hazard-free asynchronous circuits

Abstract: A teclinique for the synthesis of asynchronous sequential circuits from a Signal Transition Graph (STG) specificatmion is described. We give algorithms for synthesis and hazard removal, able to produce hazard-free circuits with the bounded wire-delay model, requiring the STG to be live, safe and to have the unique state coding property. A proof tliat, contrary to previous beliefs, STG persistency is not necessary for hazard-free implementation is given.

Multiple-processor computer system with asynchronous execution of identical code streams

Abstract: A fault-tolerant computer system employs multiple identical CPUs executing the same instruction stream, each with their own independent memory. The multiple CPUs are loosely synchronized, as by counting events such as operating cycles and stalling any CPU ahead of others. Data output references via separate busses are voted at separate ports of each of the CPUs by voting circuits which detect when all CPUs have made the same reference, and only then pass on identical references to external I/O busses. The ports may include FIFO buffers to allow output references from the asynchronous CPUs to be handled as the CPUs load the FIFOs at different times. Input data to the CPUs from the I/O busses is not voted, but is buffered to allow the CPUs to accept it at their own clock rate.

On Asynchronous Communication Semantics

Abstract: This paper presents some results concerning equational theories for an elementary calculus based on a fragment of Milner's π-calculus. The system is interesting because it realises asynchronous message passing not by extending but reducing the original fragment, while preserving the computational power. The bisimulation based on a novel asynchronous transition system is introduced and studied. Presented results include congruence of the bisimilarity for the calculus, its relationship with two other asynchronous theories based on traces and failures, strict inclusion of its synchronous counterpart in the asynchronous theory, and the method called the Icompletion that transforms two asynchronously bisimilar terms into synchronously bisimilar ones.

Unreliable failure detectors for asynchronous systems (preliminary version)

Abstract: Failure Detectors for Asynchronous Systems* (Preliminary Version) Tushar Deepak Chandra and Sam Toueg Department of Computer Science Upson Hall, Cornell University Ithaca, New York 14853 chandra, samacs. cornell. edu We introduce the concept of failure detectors for asynchronous syst ems with crash failures. We show that even with a failure detector that makes an unbounded and possibly infinite number of mistakes, we can solve the Consensus and Atomic Broadca~t problems, two fundamental paradigms of fault-tolerant computing that are known to be unsolvable in asynchronous syst ems, We characterize failure detectors in terms of their completeness and accuracy properties, and classify them in a hierarchy ordered by a reducibility relation. We present matching upper and lower bounds on the fault-tolerance of solutions to Consensus and Atomic Broadcast for members of this hierarchy.

Asynchronous disk interleaving: approximating access delays

Abstract: The performance implications of asynchronous disk interleaving are examined. In an asynchronous system, adjacent subblocks are placed independently of each other. Since each of the disks in such a system is treated independently while being accessed as a group, the access delay of a request for a data block in an n-disk system is the maximum of n access delays. Using approximate analysis, a simple expression for the expected value of such a maximum delay is obtained. The analysis approximation is verified by simulation using trace data; the relative error is found to be at most 6%. >

Control of resources in broadband networks with quality of service guarantees

Abstract: The design principles of resource control algorithms based on asynchronous time-sharing (ATS) are addressed, together with their interaction and cooperation in a wide area network environment, and a framework for evaluating the overall performance of the system is presented. The basic concepts of the ATS framework are presented, along with an overview of an architecture for joint scheduling and admission control. Scheduling mediates the low-level competition for service between cells of different classes; admission control regulates the acceptance or blocking of incoming traffic on a call-by-call basis. The performance of the scheduling algorithms is evaluated and the interaction between scheduling and admission control is quantified. A reference model for broadband networks is presented. >

Synthesis of asynchronous state machines using a local clock

Abstract: A novel, correct design methodology for asynchronous state-machine controllers is presented. The goal of this work is a design style as close to a synchronous one as possible, but with the advantages of an asynchronous method. The implementations realize asynchronous state-machine specifications using standard combinational logic, flow latches as storage elements, and a locally-generated clocking signal that pulses whenever there is a change in state. This design style allows multiple input changes which can arrive at arbitrary times. The implementations use a minimal or near-minimal number of states. It also allows arbitrary state encoding and flexibility in logic minimization and gate-level realization, so it can take advantage of systematic CAD optimization techniques. >

Run-time monitoring of real-time systems

Abstract: A model and an implementation of a run-time environment for specifying and monitoring properties of real-time systems are presented. The proposed approach supports annotating real-time programs with events that are recorded and examined at run-time. The authors provide two general methods for synchronous or asynchronous monitoring of real-time constraints. In the synchronous case, a system constraint is embedded inside a program; thus, the constraint is examined at a particular point in the execution of a real-time task. In the asynchronous case, a constraint is monitored by a separate task during the entire execution of real-time tasks. The authors also describe an implementation of a run-time monitoring toolkit as a set of library function calls in C. >

Automatic synthesis of locally-clocked asynchronous state machines

Abstract: The authors describe a novel automated design methodology for asynchronous state-machine controllers. Using a local-clocking scheme, the method allows multiple input changes and produces hazard-free designs with a minimal or near-minimal number of states. The authors present an automated program for asynchronous state machine synthesis, and describe a new heuristic for state minimization and new optimizations to improve implementations. The program is used to synthesize competitive implementations of published designs; results are compared. >

Frame switching relay for asynchronous digital network

Abstract: A frame switching relay switches frames between input and output paths by multiplexing of the paths at frame cell level. A frame is divided into cells having a constant number of bits, whereas the frames are of variable length. The switching relay only retransmits frames that have been completely written in the buffer memory. A context memory preserves the address of the first cell at the start of the writing of a frame in the buffer memory, and memorizes the address of the output path for which the frame is destined, until the frame is completely written. A checking circuit checks that the writing of the frame does not cause an "overflow" in the buffer memory, by updating the number of cells awaiting reading and respectively associated with the output paths. If there is no overflow, the address of the first cell of the frame is written in one of the address queues as a function of the destination output path address. The frame is subsequently read by incrementation of the address of the first cell until the end of the frame is detected.

The Failure of Failures in a Paradigm for Asynchronous Communication

Abstract: We develop a general framework for a variety of concurrent languages all based on asynchronous communication, like data flow, concurrent logic, concurrent constraint languages and CSP with asynchronous channels. The main characteristic of these languages is that processes interact by reading and modifying the state of some common data structure. We abstract from the specific features of the various communication mechanisms by means of a uniform language where actions are interpreted as partially defined transformations on an abstract set of states. Suspension is modelled by an action being undefined in a state. The languages listed above can be seen as instances of our paradigm, and can be obtained by fixing a specific set of states and interpretation of the actions.

On the feasibility of distributed constraint satisfaction

Abstract: This paper characterizes connectionist-type architectures that allow a distributed solution for classes of constraint-satisfaction problems. The main issue addressed is whether there exists a uniform model of computation (where all nodes are indistinguishable) that guarantees convergence to a solution from every initial state of the system, whenever such a solution exists. We show that even for relatively simple constraint networks, such as rings, there is no general solution using a completely uniform, asynchronous, model. However, some restricted topologies like trees can accommodate the uniform, asynchronous, model and a protocol demonstrating this fact is presented. An almost* uniform, asynchronous, network-consistency protocol is also presented. We show that the algorithms are guaranteed to be self-stabilizing, which makes them suitable for dynamic or error-prone environments.

Datawave: a single-chip multiprocessor for video applications

Abstract: A fine-grained MIMD (multiple-instruction, multiple-data) array processor for video applications that combines submicron technology, parallel processing, and dataflow programming is presented. The Datawave processor is used as the building block of this cellular, data-driven system architecture. The processor executes statically scheduled dataflow programs, and self-timed hardware mechanisms handle the asynchronous dataflows automatically and transparently. The architecture is discussed first at the array level and then at the cell level. It is shown how Datawave implements a four-tap finite impulse response filer and a real-time image codec. Program development tools for Datawave are discussed, and the chip itself is briefly described. >

Simultaneous scheduling and allocation for cost constrained optimal architectural synthesis

Abstract: An integer programming (IP) model, which simultaneously schedules and allocates functional units, registers, and busses, is presented for synthesizing cost-constrained globally optimal architectures. This research is important for industry by providing optimal schedules which minimize interconnect costs and interface to analog and asynchronous processes, since these are seen as key to synthesizing high performance architectures. A partially structured tight IP formulation of the architectural synthesis problem provides globally optimal schedules for peicewise linear cost functions, using branch and bound, in execution times faster than previous research. This research breaks new ground by 1. simultaneously scheduling and allocating hardware resources including interconnect, 2. support for asynchronous and analog interfaces, and 3. guaranteeing globally optimal solutions in practical execution times.