Showing papers on "Automatic test pattern generation published in 1985"

Built-In Self-Test Techniques

Abstract: A system that includes self-test features must have facilities for generating test patterns and analyzing the resultant circuit response. This article surveys the structures that are used to implement these self-test functions. The various techniques used to convert the system bistables into test scan paths are discussed. The addition of bistables associated with the I/O bonding pads so that the pads can be accessed via a scan path (external or boundary scan path) is described. Most designs use linear-feedback shift registers for both test pattern generation and response analysis. The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.

Statistical Fault Analysis

Abstract: Statistical Fault Analysis, or Stafan, is proposed as an alternative to fault simulation of digital circuits. This method defines Controllabilities and observabilities of circuit nodes as probabilities estimated from signal statistics of fault-free simulation. Special Procedures deal with these quantities at fanout and feedback nodes. The computed probabilities are used to derive unbiased estimates of fault detection probabilities and overall fault coverage for the given set of input vectors. Among Stafan's advantages, fault coverage and the undetected fault data obtained for actual circuits are shown to agree within five percent of fault simulator results, yet CPU time and memory demands fall far short of those required in fault simulation. The Computational complexity added to a fault-free simulator by Stafan grows only linearly with the number of circuit nodes.

PROTEST: A Tool for Probabilistic Testability Analysis

Abstract: The CAD-tool PROTEST (Probabilistic Testability Analysis) is presented PROTEST estimates for each fault of a combinational circuit its detection probability which can be used as a testability measure Moreover it calculates the number of random test patterns which must be generated in order to achieve the required fault coverage It is also demonstrated that the fault coverage will increase and the necessary number of random patterns will drastically decrease, if each primary input is stimulated by test patterns having specific probabilities of being logical "1" PROTEST uses this fact and determines for each input the optimal signal probability for a randomly generated pattern

Built-In Self-Test Structures

Abstract: A system that includes self-test features must have facilities for generating test patterns and analyzing the resultant circuit response. This article surveys the structures that are used to implement these self-test functions. The various techniques used to convert the system bistables into test scan paths are discussed. The addition of bistables associated with the I/O bonding pads so that the pads can be accessed via a scan path (external or boundary scan path) is described. Most designs use linear-feedback shift registers for both test pattern generation and response analysis. The various linear-feedback shift register designs for pseudorandom or pseudoexhaustive input test pattern generation and for output response signature analysis are presented.

A Practical Approach to Fault Simulation and Test Generation for Bridging Faults

Abstract: In this correspondence we prepent a practical approach to fault simulation and test generation for bridging faults in combinational circuits. Unlike previous work, we consider Unrestricted bridging faults, including those that introduce feedback. Our approach is based on extending fault simulation and test generation for stuck faults to cover bridging faults as well. We consider combinational testing only, and show that adequate bridging fault coverage can be obtained in most cases without using sequences of vectors.

Implementing a Built-In Self-Test PLA Design

Abstract: An NMOS implementation of a new built-in self-test PLA design is presented. The layouts for its additional test circuitry result in appoximately 15-percent overhead for most large PlAS, a significantly better overhead than that of any existing scheme. Both the input test patterns and the output responses, which are compressed intoastring of parity bits, are independent of the functions that the PLA realizes, and the 15-percent overhead includes the storage needed for the fault-free compressed output data. The fault coverage of this approach consists of all single and (1-2 -( 2n + m)) of all multiple stuck, crosspoint, and bridging faults in the original PLA and the additional test circuitry (n and m are the number of input variables and product terms, respectively). The article begins with a short review of existing design schemes.

Test Length in a Self-Testing Environment

Abstract: Two ideas are Coupled to help determine the Pseudorandom test length in a self-testing environment. The first is that yield, defect level after test, and test coverage are related. Tbe second is that Fault Coverage as ta function of the number of pseudorandom test patterns can be approximated on semilogarithmic paper an exponential curve, with statistical confidence intervals. Merging these two concepts allows one to relate the shipped defect level as a function of the number of radomp pattterns and yield, With this knowledge, the test length of pseudorandom patterns Can be Predicted in a self-test environment.

A Self-Testing Dynamic RAM Chip

Abstract: A novel approach to making very large dynamic RAM chips self-testing is presented. It is based on two main concepts on-chip generation of regular test sequences with very high fault coverage, and concurrent testing of storage-cell arrays to reduce overall testing time. The failure modes of a typical 64K RAM employing one-transistor cells are analyzed to identify their test requirements. A comprehensive test generation algorithm that can be implemented with minimal modification to a standard cell layout is derived. The self-checking peripheral circuits necessary to implement this testing algorithm are described, and the self-testing RAM is briefly evaluated.

Design of Testable CMOS Logic Circuits Under Arbitrary Delays

Abstract: The sequential behavior of CMOS logic circuits in the presence of stuck-open faults requires that an initialization input followed by a test input be applied to detect such a fault. However, a test set based on the assumption that delays through all gates and interconnections are zero, can be invalidated in the presence of arbitrary delays in the circuit. In this paper, we will present a necessary and sufficient condition for the existence of a test set, which cannot be invalidated under arbitrary delays, for an AND-OR or OR-AND CMOS realization for any given function. We will also introduce a Hybrid CMOS realization which, for any given function, is guaranteed to have a valid test set under arbitrary delays.

Automatic Design for Testability Via Testability Measures

Abstract: In this paper we present a technique for the automatic design for testability of digital circuits based upon the analysis of controllability and observability measures. The new concept of sensitivity is introduced, which is a measure for the degree to which the testability of a circuit improves as increased controllability and observability is achieved over a set of nodes in a circuit. In order to improve the testability of a circuit, three simple transformations are used, namely, the addition of a new primary input and possibly an AND (OR) gate so that a logic 0(1) can be injected into the interior of the circuit, and test points so that internal signal values can be observed. We then introduce the global r-modification problem, which deals with making r (integer) transformations to a circuit in order to improve its testability. This resynthesis problem has been formulated as a mixed integer linear programming problem. A program called Testability Improvement Program (TIP) has been developed for implementing this approach, and experimental results are presented. The work presented is applicable to problems of test generation, the design of fixtures for ATE, and determining the location of test pads on integrated circuit chips when employing electron beam testing.

Simplified delay testing for LSI circuit faults

Abstract: Thorough delay testing of a combinational logic circuit is accomplished by changing only one input at a time (a single transition), and checking the output at a predetermined short time later, and arrangements are disclosed for systematically applying to the inputs of a combinational logic circuit all possible single transitions of the binary input signals. One economical test circuit uses a conventional binary counter and an associated ring counter to generate the test signals, in addition to input switching circuits or multiplexers for steering data to the logic to be tested and control circuitry to control the test process.

On the implementation of an analog ATPG: the nonlinear case

Abstract: In order to reduce the complexity of the fault diagnosis equations and still retain computational simplicity, a self-testing algorithm has been proposed and implemented on a VMS VAX 11/780 for linear circuits. A prototype implementation of such an algorithm for nonlinear circuits and systems is presented. The proposed analog automatic test program generator (AATPG) for nonlinear circuits and systems is divided into offline and online processes. Unlike the simulation of the pseudocircuits in the linear case, which can be achieved by a matrix/vector multiplication, the circuit simulator SPICE is used to simulate the nonlinear pseudocircuits. The automatic SPICE code generator required for this simulation is presented. The proposed AATPG for nonlinear circuits has been implemented on a VMS VAX 11/780. The actual test can be run in either a fully automatic mode or interactively. >

A measure of test case completeness (software, engineering)

Abstract: When testing a computer program, it is not usually clear when to stop testing and, at the same time, have some level of assurance that the program is correct. This decision, as well as the selection of test cases, is often done in an ad hoc manner. This dissertation addresses a technique that can be used to gain assurance that the quality of test cases are improving. First, a metric is developed to measure the effectiveness of a set of test cases developed using a particular testing approach, such as statement coverage, branch coverage, multiple condition coverage, path testing, cause-effect graphing and mutation analysis. A single measurement approach for test cases is developed, regardless of the test approach used to generate the test cases. This metric is used to evaluate both structural and functional methods for generating test cases. Next, a composite metric is constructed based on metrics developed for the approaches that were evaluated. This composite metric is shown, for the examples studied, to increase as the number of errors discovered increases. That is, by adding more test cases in a manner that increases the composite metric, one is likely to find more program errors than by adding test cases in a random manner. In addition, by applying regression analysis, some of the components of the composite metric are shown to be a predictor of the reliability of the programs in the sample studied. It is also shown that the cause-effect graphing and equivalent normal form approaches to test case generation produce the same test cases. The equivalent normal form method is more algorithmic and easier to implement.

Method for test generation

Abstract: A method for providing test vectors adapted to test very large scale integrated circuit devices includes the steps of measuring testability employing a test counting procedure to provide a plurality of test count matrices. Sensitivity values are then enumerated by driving individual sensitivity values forwardly and rearwardly through the circuit, starting at the input terminals, until the test counts are accumulated. The enumerations define test vectors capable of testing the actual circuit. If the circuit includes reconvergent fanout loops, then these loops are enumerated first to provide partial solutions adopted during subsequent global enumeration.

Hierarchical test system architecture

Abstract: A hierarchical complex logic tester architecture is disclosed which minimizes the encoding of program information for testing. The architecture takes advantage of the fact that much of the information applied as test signals to pins of a device under test, changes little from test cycle to test cycle. In one aspect of the invention, run length encoding techniques are used for identifying the number of test cycles over which a given test pin is to be maintained in a particular signal state. In another aspect of the invention, use is made of a small memory associated with each signal pin of the device to be tested. There may be a small plurality of for example, 16 different kinds of signals which can be applied to or received from a given signal pin of a device under test. The dedicated small memory associated with each device pin to be tested, will have the ability to store from one to 16 states. The current states stored in a dedicated-per-pin memory will enable one of the 16 different types of test signals per test cycle to be applied to the particular device pin. Thus, the types of signal driving or sensing for each of the plurality of pins for a device under test, need only be indicated once to the per-pin-memory over a large plurality of test cycles. This enables consecutive test cycles to be applied to the device under test under the control of a relatively small number of tester program words.

The S-Algorithm: A Promising Solution for Systematic Functional Test Generation

Abstract: We present a new algorithm for functional test generation of VLSI systems. This algorithm for functional test generation for each testable register-transfer (RT) level fault defined in our established fault model. The technique developed is appropriate for test generation in top-down Computer-Aided Design process. The development of the algorithm is based on two foundations: the RT-level fault model and symbolic execution technique. A well-defined RT-language for the functional representation of a digital system is described. Based on this language, the RT-level fault modeling and fault collapsing analysis are performed. The fault model is established to lay an analytical foundation for the investigation of faulty behavior among RT-level fault types. The RT-level symbolic execution technique is used to derive test patterns during test generation. Major problem areas are defined and appropriate solutions are presented. The whole test generation process is divided into three stages: preprocess, the S-algorithm, and post-process. "Divide and conquer" principle is used throughout the test generation process for systematic problem solving. The S-algorithm is the heart of the overall algorithm. It performs test pattern generation based on the reduced fault model using machine symbolic execution. This test generation algorithm has been implemented in PASCAL on IBM 370/168.

RTG: Automatic Register Level Test Generator

Abstract: The Register level Test Generator (RTG) system is a software tool that automatically develops test patterns to detect all classical single “stuck-at” faults in a digital circuit. In its current state RTG is targeted for boards containing SSI, MSI, and small LSI components. RTG combines an efficient technique for modeling sequential components at the register level with a simple set of testability design rules, and a powerful test generation algorithm. Thus far in its development RTG has been shown to be a useful tool, typically capable of generating a 100% fault coverage test for a 50 IC board in about 30 CPU minutes on a VAX1 11/780 running UNIX.2

Functional Fault Modeling and Simulation for VLSI Devices

Abstract: Functional fault modeling and simulation for VLSI devices is described(*). A functional fault list is compiled using model perturbation and mapping of circuit defects into functional faults. A set of test vectors is then derived which detects all faults in the functional fault list. This same test vector set is then applied to a gate level model of the device. For the test case analyzed, a very high level of equivalent gate coverage was achieved. Conclusions are drawn as to the effectiveness of the technique and how amenable it is to automation.

MIND: An inside Look at an Expert System for Electronic Diagnosis

Abstract: Because of its intended purpose, it is very complicated to diagnose faults in VLSI test system hardware. When this problem is considered in the hardware design phase, it is apparent that VLSI test systems need to have built-in self-test features. For a self-test to be of any value, the circuit check program should minimize the hardware involved in each test. MIND is an expert system for VLSI test system diagnosis that integrates the principles of their hierarchical design and experts' heuristics to achieve a practical approach to reducing test system downtime.

Functional test generation of digital lsi/vlsi systems using machine symbolic execution technique (fault model, register transfer)

Abstract: Functional testing is among the promising solution proposed in recent years for the challenging problems of testing modern digital LSI/VLSI systems It is aimed at validating the correct operation of a digital system with respect to its functional specification Functional test generation is performed before functional testing In this dissertation, a functional test pattern generation algorithm is developed This algorithm is explicit, systematic and practical The whole research work consists of five related topics including theoretical development and computer experiment First, a register transfer language specially designed for the functional description of a general digital system is defined Second, a register-transfer (RT) level fault model quite different from the conventional gate-level stuck-at fault model is established and the fault collapsing analysis is performed for better test generation efficiency Third, the technique of register-transfer-level symbolic execution is explored The major problems are defined, analyzed, and solved A register-transfer-level symbolic execution system is designed and implemented Fourth, an overall RT-level test pattern generation algorithm is developed based on the RT-level fault model and the RT-level symbolic execution technique The symbolic executions are performed on both fault-free and fault-injected machines for symbolic results By comparing the symbolic results and path constraints obtained from fault-free and fault-injected machines, an input test pattern which distinguishes each "bad" machine from the "good" machine is derived Finally, an experimental computer implementation of the major parts of the test generation algorithm is set up Its performance is measured by several examples The experiment demonstrates that the functional test generation technique is both practical and feasible By using valuable skill developed in software testing for hardware testing, this technique is automation-oriented and hence provides a promising solution for the testing problems of modern VLSI systems

High level hierarchical fault simulation techniques

Abstract: This paper presents techniques for simulating directly from a hierarchical circuit description without flattening to the level of primitives. An overview of traditional fault simulation techniques is followed by details of the hierarchical techniques. The fault model is shown to be decoupled from the simulator programs through the use of a fault library. The fault library allows the user to mix both functional and technology-dependent fault models, which allows fault simulation and consequently test coverage estimation early in the design, with refinements in the fault model and test coverage as the design progresses. Thus testing problems can be detected early in the design process while they are much easier to correct. The circuit description language, SCALD, and the fault library language are described and illustrated with examples. The simulator initialization and execution phases are discussed in detail with emphasis on the unique data structures necessary for hierarchical simulation. The hierarchy provides a framework for an adaptive evaluation technique that speeds the evaluation of faulty machines. Initial performance measurements and experiences with the simulator indicate that hierarchical fault simulation is superior to traditional techniques.

Review of built-in test methodologies for gate arrays

Abstract: The paper presents a review of current and proposed test methodologies for semicustom gate arrays. The necessity of high quality testing is emphasised by considering some of the hazards and penalties associated with poor testability. The usefulness and limitations of testability analysis programs are then considered. A built-in test is introduced as an attractive alternative to conventional approaches based on automatic test pattern generation for highly structured circuits. This test technique is shown to offer significant benefits, including reduced test data volume, improved test quality, and easier maintenance testing. The advantages and disadvantages of three built-in test implementations for gate arrays are discussed. First, an architecture which combines an ad hoc design for testability with a comprehensive on-chip maintenance system is reviewed. This is followed by a presentation of an LSSD-based pseudorandom self-test and the associated test problems. Finally an exhaustive test, based on a similar architecture achieves a high quality test with guaranteed fault coverage. In conclusion, the future direction of test strategy development is predicted, in the context of increasing integration density and the convergence of `semicustom? and `full-custom? design styles.

Device for translating a test sequence to a burn-in sequence for a logic circuit and/or a digital circuit, a method for burn-in operation of a logic circuit and/or a digital circuit

Abstract: In order to translate a test sequence into a sequence for burn-in operation of integrated logic circuits and digital circuits, the invention provides a method and a device for automatic translation of a test truth-table into a burn-in truth-table. In addition to the reduction in cost achieved by automatic generation of test sequence, a test performed after burn-in operation of a circuit permits reliable detection of a circuit fault since the same type of sequence is adopted both for burn-in and for testing.

Self-Tested Data Flow Logic: A New Approach

Abstract: The article describes a new approach to the self-testing and testability analysis of the types of logic structure encountered in the data flow paths of computers. The main purpose of the new methodology is to avoid the costs associated with manual or automatic test pattern generation. Instead of relying upon an automated process of scanning through a gatelevel description of the logic, this is an analytical approach applied to a block-level functional description of the logic structure. This approach allows a hybrid test technique to be adopted, based on both random and pseudoexhaustive test styles, and gives fault coverage figures in excess of 99.5 percent. The methodology is suitable only for highly structured and well-partitioned logic designs.

Functional Reasoning for Fault Diagnosis Expert Systems

Abstract: Functional Reasoning for Fault Diagnosis Expert SystemsRobert MilneHeadquarters Department of the Army Artificial Intelligence CenterHQDA DAIM -DO, The Pentagon, Wash DC 20310AbstractIndustry today has a severe problem in the automatic testing of analog cards. At the AirForce Institute of Technology, we are developing an Expert System based on the structure andfunction of an analog circuit card to drive automatic test equipment. This system uses theinformation contained in the schematic diagram of the circuit as well as fundamentalknowledge of electronics and past experience in maintaining the card. One of the mostimportant aspects of this system is its ability to reason about possible faults based uponthe function of the sub -sections of the circuit. This task is accomplished using the typeof "second principles" which an electronic engineer would use. It generates which tests thetest equipment will conduct and, based upon the results of these test, determine the besttest to perform next. In this paper, the basic reasoning mechanism for these systems isdiscussed.IntroductionTesting and fault diagnosis of printed circuit cards is a very important task which isdone many times each day. Typically this is performed using pre- determined, static andrigidly structured tests. As a result, the testing tends to be inefficient, missing manyfaulted components and can often isolate faults to only a large group of components.We introduce the "theory of responsibilities" as an approach to automatedtroubleshooting. Using this approach, the understanding of how a circuit works is recordedby assigning responsibilities for parts of the output waveform to subsections of thecircuit.Our current efforts are directed at automated troubleshooting of analog circuit cards.Our overall system, described in [5] and [6], is designed to automatically test and identifyfaults in an analog card through the use of automatic test equipment. Our pastimplementation and papers have conducted testing based on the structural description of thecircuit. In this paper, our approach to functional testing is described.This work differs from others in several significant ways. The work of Cantone [1] hasbeen entirely within the structural area. His algorithm for deciding which test to performbased on the most information gained and possible cost is very helpful to structuralreasoning, but can't help us once we can no longer probe within an sub -circuit. Cantoneonly uses structural information to isolate the fault to a single functional area. In thispaper, we will show how structural information can be used to further propose faults.Dekleer [3] is working to diagnose faults in analog circuit cards from 'firstprinciples'. That is, given the low level electronic description of how a capacitor works,it should be possible to deduce how a filter would work, and consequently, diagnose faults

A Microprocessor Test Approach Allowing Fault Localization.

Abstract: An approach allowing functional diagnoses to be stated when testing microprocessors is presented. The approach is implemented on a behavioral test dedicated system: the GAPT system. It is illustrated by results obtained during the test of samples of a second source of the 80C86 microprocessor.