Showing papers on "Block (data storage) published in 1980"

A cryptanalytic time-memory trade-off

Abstract: A probabilistic method is presented which cryptanalyzes any N key cryptosystem in N^{2/3} operational with N^{2/3} words of memory (average values) after a precomputation which requires N operations. If the precomputation can be performed in a reasonable time period (e.g, several years), the additional computation required to recover each key compares very favorably with the N operations required by an exhaustive search and the N words of memory required by table lookup. When applied to the Data Encryption Standard (DES) used in block mode, it indicates that solutions should cost between 1 and 100 each. The method works in a chosen plaintext attack and, if cipher block chaining is not used, can also be used in a ciphertext-only attack.

Locally optimal block quantizer design

Abstract: Several properties are developed for a recently proposed algorithm for the design of block quantizers based either on a probabilistic source model or on a long training sequence of data. Conditions on the source and general distortion measures under which the algorithm is well defined and converges to a local minimum are provided. A variation of the ergodic theorem is used to show that if the source is block stationary and ergodic, then in the limit as n → ∝, the algorithm run on a sample distribution of a training sequence of length n will produce the same result as if the algorithm were run on the “true” underlying distribution.

Data flow component for processor and microprocessor systems

Abstract: A Large Scale Integration (LSI) data flow component is described for use as a building block, the component being capable of use singly or in combination to provide data flow paths and functions of different data widths for a processor or microprocessor. A component with an eight-bit data flow is described as a "byte slice", wherein individual byte control is provided within a multiple-byte configuration so that single data flow components within the group can operate independently of other components under control of external logic. Components may operate on a stand-alone, a multiple-byte, or nonactive-byte basis. A control scheme permits functions of one component to be influenced by actions or logic of another component to permit efficient implementation of arithmetic algorithms.

Reduced order modelling and control of two-time-scale discrete systems†

Abstract: A class of linear shift-invariant discrete systems satisfying a two-time-scale property is defined and a model satisfying this property is given. A pair of explicitly invertible block diagonalizing transformations are used to obtain reduced order fast and slow models analogous to the continuous singularly perturbed case. A deadbeat approximation to the fast modes results in a reduced order slow model, and a ‘ boundary layer ’ error in the original fast states. For control law design, the dual nature of these block diagonalizing transformations allows partial or total eigenvalue placement for fast and/or slow modes based on feedback designs for the reduced order slow and fast models.

Partial-match retrieval using indexed descriptor files

Abstract: In this paper we describe a practical method of partial-match retrieval in very large data files. A binary code word, called a descriptor, is associated with each record of the file. These record descriptors are then used to form a derived descriptor for a block of several records, which will serve as an index for the block as a whole; hence, the name “indexed descriptor files.”First the structure of these files is described and a simple, efficient retrieval algorithm is presented. Then its expected behavior, in terms of storage accesses, is analyzed in detail. Two different file creation procedures are sketched, and a number of ways in which the file organization can be “tuned” to a particular application are suggested.

Data processing system integrated circuit having modular memory add-on capacity

Abstract: A method of designing and manufacturing a modular integrated circuit for a 4 bit microcomputer family utilizing a modular concept which is adaptable for a variety of applications and specific circuit desgins. The modular circuit is designed as a large block of cells which contains an ALU, instruction decoder, bus structure and a small amount of RAM and ROM as well as ROM control logic. In addition, the block contains attachment points for additional ROM and RAM and for special input/output devices such as I/O bus, timekeeping, A-D, D-A, display drive, communication ports and general purpose control lines.

Flow control mechanism for block switching nodes

Abstract: In a communication network comprising block switching nodes interconnected by transmission links, a flow control mechanism is provided in each switching node for regulating the flow of addressed data blocks or messages. A hardware look-ahead mechanism effective within each node tests for each data block received from a link and buffered at an input port, whether it can be accepted at the appropriate output port of the same node for further transmission. A token mechanism effective over links permits maintenance at each output port of a node of an indication whether any data block can be accepted in the input port at the other end of the respective link. By the combined operation of look-ahead mechanisms and token mechanisms the flow of addressed messages in a direction where the transmission path is already filled up is prevented. This has a positive smoothing effect on overall traffic flow where short-time or local overloads occur.

Inter-subsystem communication system

Abstract: A communication system operation between computer systems which realizes highly efficient data transfer in a data processing system has sender and receiver subsystems operating under the control of an independent or common operating system. The communication system also includes: a plurality of sending buffers, a sending buffer address table having a plurality of entries and a buffer control block in the sender subsystem and a plurality of receiving buffers, a receiving buffer address table having a plurality of entries and a buffer control block in the receiver subsystem, and the communication path for transferring the data stored in the sending buffer to the receiving buffer.

Design Considerations for Single-Chip Computers of the Future

Abstract: In the mid 1980's it will be possible to put a million devices (transistors or active MOS gate electrodes) onto a single silicon chip. General trends in the evolution of silicon integrated circuits are reviewed and design constraints for emerging VLSI circuits are analyzed. Desirable architectural features in modern computers are then discussed and consequences for an implementation with large-scale integrated circuits are investigated. The resulting recommended processor design includes features such as an on-chip memory hierarchy, multiple homogeneous caches for enhanced execution parallelism, support for complex data structures and high-level languages, a flexible instruction set, and communication hardware. It is concluded that a viable modular building block for the next generation of computing systems will be a self-contained computer on a single chip. A tentative allocation of the one milion transistors to the various functional blocks is given, and the result is a memory intensive design.

Buffer memory referencing system for two data words

Abstract: A memory accessing system for reading or writing consecutive addressable words is described for use in a set associative memory system. Two high speed buffer memories store words read in blocks from a slower main memory. One buffer stores even addressed words and the other stores odd addressed words. Each buffer memory has a tag memory associated with it for indicating data words stored in the buffer memories. A comparison circuit compares two addresses to be accessed to the tags and provides hit or miss signals for each address indicating residency or non-residency in the buffers. If both addressed words are resident, access to read or write the two consecutive data words is accomplished simultaneously. If either or both addressed words are not resident in the buffers, the main memory is accessed to acquire a block or blocks containing the missing addressed word or words. Consecutively addressed data words can occur within a block or across block boundary. The system examines the addresses and gives an indication when a block boundary crossing is to occur, and provides accessing to read or write sequentially addressed data words across the block boundary crossing simultaneously.

Design Considerations for Single-Chip Computers of the Future

Abstract: In the mid 1980's it will be possible to put a million devices (transistors or active MOS gate electrodes) onto a single silicon chip. General trends in the evolution of silicon integrated circuits are reviewed and design constraints for emeging VLSI circuits are analyzed. Desirable architectural features in modem computers are then discussed and consequences for an implementation with large-scale integrated circuits are investigated. The resulting recommended processor design includes features such as an on-chip memory hierarchy, multiple homogeneous caches for enhanced execution parallelism, support for complex data structures and high-level languages, a flexible instruction set, and communication hardware. It is concluded that a viable modular building block for the next generation of computing systems will be a self-contained computer on a single chip. A tentative allocation of the one million transistors to the various functional blocks is given, and the result is a memory intensive design.

Multiplexed data communications using a queue in a controller

Abstract: A data communications controller, for use intermediately between a data processor and a data communications link such as a modem driven land line, relieves the data processor of time-consuming supervisory and data preparation tasks, normally associated with the use of a data link, by means of a block loadable transmit queue, an automatic cyclic redundancy check generator, an automatic time fill generator and a parity generator, a block unloadable receive queue, an automatic character translator, an automatic character monitor and a received serial bit queue in conjunction with a byte synchronizing detector, the operation or non-operation of each of the above elements and, if operational, the manner of that operation, being selectable by commands from the data processor, the commands from the data processor being intermingled with but distinguishable from data to be sent over the data link.

On Block-Parallel Methods for Solving Linear Equations

Abstract: An MIMD-type parallel-processing system was introduced recently. Using an extended PL/I notation, algorithms for the Gauss-Seidel method and for back substitution are written for this system. Block execution is shown to result in higher speedups.

Data processing system with data cross-block-detection feature

Abstract: A data processing system is disclosed in which it is detected whether or not data to be read out from a buffer memory with a single access are spread over a plurality of blocks, which are used as the unit for storing data in the buffer memory, and, when the presence of block cross is detected, addresses of blocks including a desired operand are generated as addresses in banks making up the buffer memory, whereby the operand is read out from adjacent blocks by a single read-out operation.

System for formatting data on video tape for high accuracy recovery

Abstract: A system for formatting data on video tape for high accuracy recovery in which binary data is recorded on the video signal track of video tape in a prearranged format of three redundant blocks of data words between successive vertical sync pulses. Each redundant block of data words is preceded by a set of at least three redundant sync words and the last block of data words is followed by a fourth set of redundant sync words. The redundant sync words in each set are separated from each other by a plurality of blank horizontal sync pulse intervals. Circuitry for recovering data in this format is disclosed together with a system for writing data in this format.

Index information recording method for picture information filing system

Abstract: In a picture information filing system using an endless magnetic tape (43), which has a plurality of picture information recording tracks (48 2 ) for a plurality of units of recording two-dimensional picture information (3) in predetermined blocks and an index information recording track (48 1 ) for recording index information for the individual unit picture information, the index information is temporarily stored in a random access memory (13) as unit index information groups each consisting of a predetermined number of index information items, recording start index information consisting of a peculiar code and an address representing the position from which to record the next picture information is added to the last index information item in the last index information group, and the individual index information groups are recorded in predetermined blocks of the index information recording track, each index information group in each particular block.

Determination of effective well block radii for numerical reservoir simulations

Abstract: In the numerical simulation of underground reservoir behavior it is often necessary to employ well blocks (i.e., a grid block containing a well) with dimensions much larger than the well diameter. This paper develops practical procedures for making reasonable estimates of well bore sandface conditions from the well block conditions calculated by numerical reservoir simulations. It is assumed that on a sub-grid scale, pressures will equilibrate much more rapidly than in the reservoir as a whole; the subgrid flow may therefore be treated as steady flow. The conditions at the sandface may then be deduced from mean well block conditions by assuming that the latter obtain at a definite distance (the ‘effective well block radius’) from the well. The problem is to establish the value of the effective well block radius in terms of the size of the well block and other relevant parameters. Grid pressures obtained in the numerical solution of liquid flow into a single well located in both radial and rectangular grid blocks are examined. It is found that the effective well block radius depends on, among other things, the shape of the grid block (radial or rectangular), the type of mesh (uniform or otherwise) employed, and the character of the spatial discretization scheme.

Fuel feeding device of internal combustion engine

Abstract: PURPOSE:To improve driving stability at the time of engine start, by computing fuel to be fed through averaging engine parameters or their operated values of revolution at low gear operation, load, etc. CONSTITUTION:In a block for computing fundamental fuel injection (Tp) from suction air (Q) and engine revolution (N), virtual fundamental fuel injection (Tp') is handled as fundamental one (Tp) without modification when the engine revolution (N) exceeds about 450rpm, but is computed with an exponential averaging expression (Tp)=(2 -1)Tpo/2 +Tp'/2 using a fundamental fuel injection (Tpo) which is the amount a round (10ms) in advance of the interative calculation. This can keep the fluctuation of fuel feed small during the low gear operation or at the engine start, thus stabilizing the driving performance.

Memory checking method

Abstract: A method of checking a memory in a computer system having memory for storing at least one logical block composed of a plurality of words, and a processor for retrieving data from the memory to perform a memory check wherein the method includes inserting an operational control word into the logical block in advance, sequentially subjecting each word in the logical block to a prescribed operation, such as an exclusive-OR operation applied to corresponding ones of the bits in each word, and then determining whether or not the result of the operation is the same as a predetermined value. The operational control word, before being inserted into the logical block, is determined in such a manner that the result of the operation will be equivalent to a predetermined value, such as all "0"s.

Buffer storage control apparatus

Abstract: A buffer storage control apparatus selectively employs the conventional "least-recently-used" (LRU) algorithm or the "all-used" (AU) algorithm to determine which block of data in the buffer storage unit is to be replaced by new data. The AU algorithm relies on the fact that under certain conditions, such as the straight transfer of a block of data from a main memory to an output device under the control of an I/O supervisor, the block of data so transferred will no longer be needed. The control apparatus therefore detects such a data transfer and selectively allocates buffer storage in accordance with the AU or LRU algorithms.

System capacity and performance evaluation

Abstract: The performance of MVS (Multiple Virtual Storage) systems can be predicted for changes in workload and environment by an IBM marketing aid informally called SCAPE (for System Capacity and Performance Evaluation). Written in FORTRAN, the programs use simple queuing formulas with empirical modifications. Response times for complex workload(IMS, CICS, TSO, and batch) through the CPU and auxiliary storage are expressed as functions of application loads and other parameters that define the system's environment. SCAPE can predict the effect on performance of different CPU models, larger memory, additional channels, additional direct-access storage, larger block sizes, and alternate workload projections.

Digital data acquisition and analysis of striated muscle diffraction patterns with a direct memory access microprocessor system.

Abstract: A microprocessor based data acquisition computing system has been developed to examine dynamic changes in light diffraction patterns from single skeletal muscle fibers. A significant improvement in digital data acquisition rate compared to previous designs has been achieved by utilizing a fast dedicated analog to digital converter and direct memory access data storage. Diffraction patterns from muscle fibers are imaged onto a 256 element charge‐coupled device. The analog output of a full 256 point frame of data may be digitized and stored in 2.2 ms (128 point half frame in 1.1 ms) with a spatial resolution of up to 5.0 nm/sarcomere. This computing system can transfer up to 28 full frames of data as one continuous block directly between the CCD and memory leaving the CPU free for experimental control and closed‐loop processing. The computing system calibrates and analyzes diffraction data under sofware control for sarcomere length, dispersion, and peak intensity. The operation of this data acquisition comp...

A Neighbor Connected Processor Network for Performing Relational Algebra Operations

Abstract: In a data base computer consisting of cells with processing capability, the desired goal is to achieve an execution time - for each data base operation - to be inversely proportional to the number of cells. Using rings as a basic building block, we have constructed different intercell communication networks. The capacity of the communication network have been analyzed under the workload of relational algebra operations. A k-dimensional network of intersecting rings, each of 2 or 3 cells have been found to give the highest processing capacity per cell in the network. Here k is log2C, where C is the total number of cells.A simple wiring scheme for k-dimensional network of 2 cells per ring has been presented. For this type of network, we have also described the routing logic, and given an estimate of the queueing delay.

Buffer memory control system

Abstract: PURPOSE:To enhance the rate of hit by prefetching the memory block having high probability to be made access subsequently in accordance with the directivity of the word address in the case where plural numbers of access are carried out in the same memory block CONSTITUTION:When the address block in the present memory access address stored in the register 10 coincides with the previous address block of the register 12, output of the comparator 14 is inverted into high level The word address in the present memory access address of the register 11 is compared with the previous word address of the register 13 by the comparators 15, 16 and in accordance with the directivity of the word address, the output of the comparators 15 or 16 becomes a high level Then, the inverted gates 21, 22, AND gates 23-26, OR gates 27, 28, FF17-20, etc are controlled and in accordance with the directivity of the word address in the case where plural numbers of access are made to the same memory block, the memory block having high probability to be made access in the next time through FF17, or 19 is fetched and the rate of hit becomes high

Multiresolution Pixel Linking For Image Smoothing And Segmentation

Abstract: When an image is smoothed using small blocks or neighborhoods, the results may be somewhat unreliable due to the effects of noise on small samples. When larger blocks are used, the samples become more reliable, but they are more likely to be mixed, since a large block will often not be contained in a single region of the image. A compromise approach is to use several block sizes, representing versions of the image at several resolutions, and to carry out the smoothing by means of a cooperative process based on links between blocks of adjacent sizes. These links define "block trees" which segment the image into regions, not necessarily connected, over which smoothing takes place. In this paper, a number of variations on the basic block linking approach are investigated, and some tentative conclusions are drawn regarding preferred methods of initializing the process and of defining the links, yielding improvements over the originally proposed method.© (1981) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

Time division switching system

Abstract: A time division multiplex (TDM) switching network is disclosed in which at least part of the network comprises a space switching portion (TMS) and in which the need for duplication of the space switching portion, and like methods of achieving network reliability, is eliminated. Data from an incoming channel is partitioned into successive blocks, a prescribed number of which form a set of blocks. The blocks are of predetermined size. Each of the blocks of a set is switched via different paths of the space portion of the network. A single network fault can therefore cause the loss of only one block of data in a set. This loss can be made insignificant in the case of data representing telephone conversations. For data not representing telephone conversations, error checking and correcting information is added to the set before transmission through the space portion of the network and errors occurring during transmission are corrected thereafter.

Prerecorded tapes, data storage and retrieval system for use therewith, and methods of storing and retrieving binary data words

Abstract: A system for formatting data on video tape for high accuracy recovery in which binary data is recorded on the video signal track of video tape in a prearranged format of three redundant blocks of data words between successive vertical sync pulses. Each redundant block of data words is preceded by a set of at least three redundant sync words and the last block of data words is followed by a fourth set of redundant sync words. The redundant sync words in each set are separated from each other by a plurality of blank horizontal sync pulse intervals. Circuitry for recovering data in this format is disclosed together with a system for writing data in this format.

Transmission system of audio packet

Abstract: PURPOSE:To increase the efficiency of packet transmission network, by avoiding to transmit the packet including the audio belonging to no sound. CONSTITUTION:The audio input from the telephone set is PCM-coded into blocks, and each block is given for serial number and stored in the memory. Only sounded part is stored in the memory, but the serial number is given to the blocks independently of sound presence. Accordingly, only (1),(2)... in the audio blocks (1),(2), (3)... are stored. The blocks stored are transmitted to the packet exchange network. At the reception side, the packet received is once stored in the memory, and the serial number of packet is checked at reproduction. Natural audio is reproduced by adding the non-sound parts (3),(6)... to the missing parts.

On K-Line and $K \times K$ Block Iterative Schemes for a Problem Arising in Three-Dimensional Elliptic Difference Equations

Abstract: Novel computer architectures and a desire to solve three-dimensional problems have together aroused new interest in iterative methods for computing solutions to elliptic difference equations. Block iterative methods are particularly attractive for vector machines, such as the Cray-1. Schemes that take the basic block to be a plane reduce a three-dimensional elliptic system to two-dimensional systems, to which block methods are again applicable. We analyze the convergence rate of k-Line and $k \times k$ block iterative methods for solving these two-dimensional problems.