Showing papers on "Cascade amplifier published in 2007"

Chopper-stabilized instrumentation amplifier for impedance measurement

Abstract: This disclosure describes a chopper stabilized instrumentation amplifier. The amplifier is configured to achieve stable measurements at low frequency with very low power consumption. The instrumentation amplifier uses a differential architecture and a mixer amplifier to substantially eliminate noise and offset from an output signal produced by the amplifier. Dynamic limitations, i.e., glitching, that result from chopper stabilization at low power are substantially eliminated through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the amplifier operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. The amplifier can be used in a low power system, such as an implantable medical device, to provide a stable, low-noise output signal.

Chopper-stabilized instrumentation amplifier

Abstract: This disclosure describes a chopper stabilized instrumentation amplifier. The amplifier is configured to achieve stable measurements at low frequency with very low power consumption. The instrumentation amplifier uses a differential architecture and a mixer amplifier to substantially eliminate noise and offset from an output signal produced by the amplifier. Dynamic limitations, i.e., glitching, that result from chopper stabilization at low power are substantially eliminated through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the amplifier operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. The amplifier can be used in a low power system, such as an implantable medical device, to provide a stable, low-noise output signal.

Design of H-Bridge Class-D Power Amplifiers for Digital Pulse Modulation Transmitters

Abstract: This paper presents an H-bridge class-D power amplifier (PA) for digital pulse modulation transmitters. The class-D amplifier can be driven by two-or three-level digital signals generated by a delta-sigma modulator (DSM) and provides a linear microwave output after filtering. Within the amplifier, the pull-up and pull-down devices are driven separately to improve the amplifier efficiency by minimizing the loss associated with shoot-through current. The H-bridge class-D PA system was tested with code-division multiple-access IS-95 signals at 800 MHz. Using binary DSM signals, a drain efficiency of 31% was achieved with an output power of 15 dBm and an adjacent channel power ratio of -43 dBc. With three-level DSM signals, a drain efficiency of 33% was achieved at same output power. An analysis of the factors governing amplifier efficiency is provided.

Circuit and method for RF power amplifier power regulation and modulation envelope tracking

Abstract: A power amplifier receives an input signal and generates an amplified output signal. A switching converter generates a regulated voltage and performs power control for the power amplifier. A linear amplifier performs modulation envelope control for the power amplifier. The switching converter may be coupled in series with the linear amplifier, and this circuit may operate in one of multiple modes. For example, the linear amplifier may output a tracked voltage to the power amplifier in GSM/polar EDGE mode, and the switching converter may output the regulated voltage to the power amplifier in WCDMA/UMTS mode. The linear amplifier could also output the tracked voltage in both modes, and a selector could select the appropriate feedback voltage for the switcher. The switching converter could also provide the regulated voltage directly to the power amplifier, and the linear converter could adjust a bias of the power amplifier to provide envelope tracking.

Rf power amplifier controller circuit with compensation for output impedance mismatch

Abstract: A power amplifier controller circuit controls a power amplifier based upon an amplitude correction signal indicating the amplitude difference between the amplitude of the input signal and an attenuated amplitude of the output signal. The power amplifier controller circuit comprises an amplitude control loop and a phase control loop. The amplitude control loop adjusts the supply voltage to the power amplifier based upon the amplitude correction signal. The amplitude control loop may also compensate for impedance mismatch with the load by increasing the power delivered from the power amplifier to the load, or decrease the output power of the power amplifier upon detection of excessive power dissipation in the power amplifier. The phase control loop adjusts the phase of the input signal based upon a phase error signal indicating a phase difference between phases of the input signal and the output signal to reduce phase distortion generated by the power amplifier.

Photoelectric conversion device and image capturing device

Abstract: A photoelectric conversion device includes a pixel unit including a photoelectric converter, an amplifier arranged on the output side of the pixel unit, an output unit arranged on the output side of the amplifier, a first restriction circuit, and a second restriction circuit. The first restriction circuit restricts, between the amplifier and the output unit, a noise level read out from the pixel unit via the amplifier in reading out the noise level from the pixel unit. The second restriction circuit restricts, between the photoelectric converter and the amplifier, a noise level to be provided to the amplifier in reading out the noise level from the pixel unit.

Constant input port impedance for CATV amplifier with passive modem port

Abstract: A passive directional coupler is receptive of VoIP, Internet, and video/data signals, and is used in a CATV amplifier device to couple the video/data signals from a cable drop input port to the input terminal of an amplifier, and to passively bypass the VoIP and Internet signals to a modem port, for insuring continuous connection of the VoIP and Internet signals to the a modem of a user connected to the modem port, regardless of the loss of power to the amplifier or the failure of the amplifier, in one embodiment of the invention. In another embodiment, a switching circuit is responsive to the loss of power to the amplifier, for electrically connecting a 75 ohm resistor between a source of reference potential, and the common connection between the directional coupler and the amplifier, for maintaining a 75 ohm impedance at the directional coupler output to the common connection. In a preferred embodiment, the switching circuit also opens the common connection between the directional coupler and amplifier, upon the loss of power to the amplifier.

Design of a High-Efficiency and High-Power Inverted Doherty Amplifier

Abstract: In this paper, we present a design method for a compact inverted Doherty power amplifier (IDPA), which has high-efficiency and high-power characteristics. An optimum load matching network and an additional offset line, after the matching network of the carrier amplifier, dynamically modulate the load impedance according to the input power drive, while the conventional Doherty power amplifier uses a quarter-wave line to do it. The operational principles and design guide are provided. For experimental verification, a 50-W Doherty amplifier was designed for the pi/4 differential quadrature phase-shift keying application at the 860-MHz band. The measured performance of the IDPA was compared with that of the balanced class-AB amplifier with the same output matching network. At an output power of 50 W, the IDPA performs with 3.16 dB better adjacent channel power ratio (-28 versus -24.84 dBc) and 6.15% higher power-added efficiency (59.02 versus 52.87%) than the class-AB amplifier does.

Enhanced doherty amplifier with asymmetrical semiconductors

Abstract: The present disclosures an amplification unit which comprises a first amplifier and a second amplifier connected in parallel, the first amplifier and the second amplifier comprising semiconductor devices that are not the same amplifier design. The present application also discloses a signal input line connected to the first amplifier and the second amplifier. A signal output line is also disclosed which is connected to the first amplifier and the second amplifier.

Chopper-stabilized instrumentation amplifier for wireless telemetry

Abstract: This disclosure describes a chopper stabilized instrumentation amplifier. The amplifier is configured to achieve stable measurements at low frequency with very low power consumption. The instrumentation amplifier uses a differential architecture and a mixer amplifier to substantially eliminate noise and offset from an output signal produced by the amplifier. Dynamic limitations, i.e., glitching, that result from chopper stabilization at low power are substantially eliminated through a combination of chopping at low impedance nodes within the mixer amplifier and feedback. The signal path of the amplifier operates as a continuous time system, providing minimal aliasing of noise or external signals entering the signal pathway at the chop frequency or its harmonics. The amplifier can be used in a low power system, such as an implantable medical device. The amplifier may be used for physiological signal sensing, impedance sensing, telemetry or other test and measurement applications.

H-Bridge Class-D Power Amplifiers for Digital Pulse Modulation Transmitters

Abstract: This paper presents an H-bridge class-D power amplifier for digital pulse modulation transmitters. For the proposed class-D amplifier, the drivers of the pull-up and pulldown devices were separated to minimize power loss associated with the shoot-through currents. The amplifier can be driven by binary digital signals generated by a delta-sigma modulator directly. The H-bridge class-D power amplifier system was tested with CDMA IS-95 signals at 800 MHz. The drain efficiency of 31% was achieved with output power of 15 dBm and an ACPR of -43 dBc.

Apparatus and method for small signal sensing in an SRAM cell utilizing PFET access devices

Abstract: A method for small signal sensing during a read operation of a static random access memory (SRAM) cell includes coupling a pair of complementary sense amplifier data lines to a corresponding pair of complementary bit lines associated with the SRAM cell, and setting a sense amplifier so as to amplify a signal developed on the sense amplifier data lines, wherein the bit line pair remains coupled to the sense amplifier data lines at the time the sense amplifier is set.

Hybrid Doherty Amplifier System and Method

Abstract: One embodiment of the invention includes an amplifier system. The system comprises a digital predistortion (DPD) system configured to receive an input signal and to provide the input signal as a first digital signal component along a first amplifier path and a second digital signal component along a second amplifier path. The system also comprises a first digital-to-analog converter (DAC) configured to convert the first digital signal component to a first analog signal component and a second DAC configured to convert the second digital signal component to a second analog signal component. The system further comprises a Doherty amplifier comprising a main amplifier in the first amplifier path that is configured to amplify the first analog signal component and a peak amplifier in the second amplifier path that is configured to amplify the second analog signal component.

Output coupling capacitor free audio power amplifier dynamically configured for speakers and headphones with excellent click and pop performance

Abstract: First and second channel bridge amplifiers are dynamically configured to drive either speakers or headphones. The first channel bridge amplifier includes a first amplifier driving one end of a first speaker through a mechanical switch in a headphone-jack, and a second amplifier driving another end of the first speaker. The second channel bridge amplifier includes third and fourth amplifiers driving respective ends of a second speaker. An amplifier control circuit dynamically detects the insertion or removal of a plug in the jack and configures the amplifiers accordingly. When a plug is inserted into the jack, the mechanical switch disconnects the first speaker from the first amplifier, and the fourth amplifier is tri-stated disconnect the second speaker. The first and third amplifiers are configured to drive the first and second channels of the headphones, while the third amplifier drives the headphone common point (shield ring) as a virtual ground connection. The virtual ground connection permits the bridge amplifiers to drive either speakers or headphones without the use of output coupling capacitors. To suppress click and pop, the amplifier control circuit maintains certain amplifiers (depending on headphone or speaker mode) tri-stated until the input coupling capacitors have fully charged and an input signal is detected. In the headphone mode, the driving amplifiers are current limited, the output signal level is automatically attenuated, and the second amplifier is controlled to prevent a ground loop short circuit condition. When a ground short is detected, the second amplifier is tri-stated by the amplifier control circuit.

A 60-GHz 90-nm CMOS cascode amplifier with interstage matching

Abstract: The design of a 60 GHz cascode amplifier in a 90 nm technology is described. The amplifier uses an interstage matching to increase the gain and to provide a better power match between the common-source and the common-gate transistor of the cascode device. Both the common-source and the common-gate transistor make use of an optimized round-table layout, which minimizes all terminal resistances and thus improves the mm-wave performance of the nMOS transistors. A record fmax of 300 GHz is achieved for a 40 mum round-table nMOS in 90 nm CMOS. The cascode amplifier achieves a gain of 7.5 dB at 60 GHz with a DC power consumption of only 6.7 mW. When compared to a shared-junction cascode amplifier or a two-stage common-source cascade amplifier, the presented cascode amplifier is favorable in terms of power gain and DC power consumption

Fully differential class AB amplifier and amplifying method using single-ended, two-stage amplifier

Abstract: A fully differential amplifier includes a first single-ended current mirror type fully differential amplifier outputting a first output signal by two stage amplifying a difference between a first input signal and a second input signal and a second single-ended current mirror type fully differential amplifier outputting a second output signal by two stage amplifying a difference between the first input signal and the second input signal. A first tail of the first single-ended current mirror type fully differential amplifier and a second tail of the second single-ended current mirror type fully differential amplifier are connected to each other and the first output signal and the second output signal are differential signals.

A composite amplifier, a radio terminal and a method for improving the efficiency of the composite amplifier

Abstract: The present invention relates to a composite amplifier (3, 4, 120), a radio terminal ( 100) including such composite amplifier and to a method for improving the efficiency of such composite amplifier in particular. The composite amplifier according to embodiments of the present invention is arranged to be connected to an output combiner network (43, 53, 63, 73, 83) and to a load (49, 130). the output combiner network comprising at least one dynamically tuneable reactance (47, 48). The instantaneous efficiency of the composite amplifier (3, 4, 120) is increased by tuning the impedances/admittances seen by each of said at least two power amplifiers (41, 42, 71, 72). The amplifiers being differently driven and they may further be part of a Chireix outphasing system or a pair of a Doherty amplifier.

Minimizing Switching Noise and its Effects in Auto-Zeroed Amplifiers

Abstract: Two nulling amplifiers are used with an auto-zeroed differential amplifier. While one nulling amplifier is compensating the main amplifier, the other nulling amplifier is being zeroed for both differential mode (DM) and common mode (CM) offsets. By using two nulling amplifiers, one always connected to the main amplifier, a relatively constant open-loop gain is maintained for the main amplifier. A further improvement is make-before-break timing overlap of the switch operations between the two nulling amplifiers and the main amplifier. This ensures that the main amplifier is continuously driven by one or both null amplifiers, thereby maintaining a low impedance at the main amplifier auxiliary port. Both DM and CM offset sampling and precharging of each of the two nulling amplifiers is performed so as to substantially reduce switching glitches in the output of the main amplifier.

A 1.9-GHz Triple-Mode Class-E Power Amplifier for a Polar Transmitter

Abstract: A 1.9-GHz CMOS power amplifier for polar transmitters was implemented with a 0.25-mum radio frequency CMOS process. All the matching components, including the input and output transformers, were fully integrated. The concepts of mode locking and adaptive load were applied in order to increase the efficiency and dynamic range of the amplifier. The amplifier achieved a drain efficiency of 33% at a maximum output power of 28dBm. The measured dynamic range was 34dB for a supply voltage that ranged from 0.7 to 3.3V. The measured improvement of the low power efficiency was 140% at an output power of 16dBm

Photoelectric conversion apparatus with fully differential amplifier

Abstract: To provide a configuration including a fully differential amplifier in which decrease in a reading speed can be suppressed. A photoelectric conversion apparatus according to the present invention includes a pixel area where a plurality of pixels are arranged; an amplifier configured to amplify a signal from the pixel area; a plurality of signal paths for transmitting the signals from the pixel area to the amplifier. The amplifier is a fully differential amplifier which includes a plurality of input terminals including a first input terminal and a second input terminal to which the signals from the plurality of signal paths are supplied and a plurality of output terminals including a first output terminal and a second output terminal and the input terminals and the output terminals have no feedback path provided therebetween.

Superconducting switching amplifier

Abstract: A superconducting switching amplifier embodying the invention includes superconductive devices responsive to input/control signals for clamping the output of the amplifier to a first voltage or to a second voltage. The amplifier includes a first set of superconducting devices serially connected between a first voltage line and an output terminal and a second set of superconducting devices serially connected between the output terminal and a second voltage line. The first set and the second set of devices are operated in a complementary fashion in response to control signals. When one of the first and second sets is driven to a superconducting (zero resistance) state the other set is driven to a resistive state. In accordance with the invention, the devices of each set are laid out in a pattern and driven in a manner to enable all the devices of each set to be driven to a selected state at substantially the same time. In one embodiment, the devices in each set are superconducting quantum interference devices (SQUIDs). Four sets of superconductive devices may be interconnected to function as a differential switching amplifier. The operating voltage applied to an amplifier may be varied to provide additional shaping of the output signal.

Multiple output power mode amplifier

Abstract: A multi-mode power amplifier and an electronic device including the amplifier are described.

Mode selection amplifier circuit usable in a signal acquisition probe

Abstract: A mode selection amplifier circuit has multiple differential amplifier circuits coupled to receive input signals A, B and C. Each differential amplifier circuit is selectively operable for generating a signal output representative of an output mode with the output mode of each differential amplifier circuit selected from one of algebraic combinations of the signal inputs A - C, B - C, A - B and (A + B) /2 - C. The mode selection amplifier circuit is usable in a signal acquisition probe for providing various signal output modes to a measurement test instrument.

Bit line sense amplifier of semiconductor memory device having open bit line structure

Abstract: In an embodiment, a bit line sense amplifier of a semiconductor memory device with an open bit line structure includes sense amplifier blocks, first voltage drivers, and a second voltage driver. The sense amplifier blocks include a first sense amplifier and a second sense amplifier, each sensing and amplifying a signal difference between a bit line and a complementary bit line. The first voltage drivers apply a power source voltage to the first sense amplifier, and the second voltage driver applies a ground voltage to the second sense amplifier. The first voltage drivers are disposed for every two or more sense amplifier blocks in a bit line sense amplifier region in which the sense amplifier blocks are arranged, and the second voltage driver is disposed in a conjunction region in which a control circuit is located to control the sense amplifier blocks. Both capacitive noise and device size are minimized.

Sigma-delta based class d audio or servo amplifier with load noise shaping

Abstract: An amplifier capable of driving an analog load is provided. The amplifier can be constructed and arranged to operate as at least one circuit selected from the group consisting of a class D amplifier, voltage regulator, audio amplifier, servo amplifier, servo control, digital control, switching power supply, and switching power amplifier. The amplifier comprises a sigma delta modulator (SDM), a pulse processing circuit, an output stage, and a feedback loop. The SDM produces a plurality of noise-shaped output pulses based upon an input signal (e.g., an analog input signal) to the amplifier and an error signal. The pulse processing circuit processes at least a portion of the plurality of noise-shaped output pulses to ensure that each of the noise-shaped output pulses in the portion contains an amount of energy that is as close as possible to the amount of energy in the other pulses. The output stage is coupled to the pulse processing circuit and has first state wherein the output stage provides analog noise-shaped output energy pulses to a load and a second state where the output energy delivered is essentially zero. The feedback loop is coupled between the output stage and the SDM. The feedback loop samples the energy provided to the load during the first state by measuring the load during the second state and generates an error signal based on the difference between the sampled portion of the noise-shaped output pulses and the input signal to the amplifier.

Method of and apparatus for reducing settling time of a switched capacitor amplifier

Abstract: A method and apparatus for reducing settling time of a switched capacitor amplifier. The method includes disconnecting first and second capacitors from an amplifier. When the first and second capacitors are disconnected from the amplifier, they are charged by respective first and second input signals. The apparatus includes a plurality of sampling capacitors, each configured to sample a respective one of a plurality of signals during a sampling phase, an amplifier, and a plurality of decoupling switches configured to isolate the sampling capacitors from the amplifier during the sampling phase and to connect the plurality of sampling capacitors to the amplifier during the amplifying phase.

Inverted doherty amplifier with increased off-state impedence

Abstract: An amplifier (100) that amplifies an input signal and provides the amplified signal to a load (114) at a summing junction (110) that has a first impedance value. The amplifier includes a splitter network (102) receiving the input signal and providing a phase delayed signal and an undelayed signal; a carrier amplifier path amplifying the phase delayed signal and including a carrier amplifier (106) and a first output match network (108) coupled between the carrier amplifier and the summing node; and a peaking amplifier path amplifying the undelayed signal and including a peaking amplifier (118), a second output match network (120) coupled to the peaking amplifier, and a phase delay element (122) coupled between the second output match network and the summing node, wherein the phase delay element provides a degree of phase delay and has a designed characteristic impedance value that is larger than the first impedance value for increasing the off-state impedance of the peaking amplifier.

Method and apparatus for controlling a semiconductor optical amplifier for use in a passive optical network

Abstract: An optical amplifier including: an amplifier having an input port and an output port, which is disposed along a main signal line of the optical amplifier; a dummy laser generation circuit having an output coupled to the main signal line and operative for inputting a dummy signal into the amplifier; a first optical detector for detecting a power level of the dummy signal into the amplifier and outputting a first power level signal; a second optical detector for detecting an amplified power level of the dummy signal output by the amplifier and outputting a second power level signal; a memory device for storing calibration data regarding the gain characteristics of the amplifier; and a gain control circuit which receives inputs from the first optical detector and second optical detector, and has an output coupled to the amplifier. The gain control circuit operates to control the gain of the amplifier based on the first power level signal, the second power level signal and the calibration data.

Distributed class g type amplifier switching method related application

Abstract: An improved Class G type amplifier which switches between multiple power rails depending upon the instantaneous amplitude of the input signal versus the power rails. The low voltage (inner) amplifier includes a plurality of parallel amplifier devices, and the high voltage (outer) amplifier includes a plurality of parallel amplifier devices. A plurality of switches each couples the input signal to either a respective one of the inner amplifier devices or a respective one of the outer amplifier devices. The switches are activated sequentially, such that the switching from inner to outer amplifier devices or vice versa is staggered over some period of time. This avoids having a single, large glitch in the output, and spreads multiple smaller glitches over enough time that some of the glitch energy can fall within the frequency range where the amplifier's feedback circuitry can eliminate its noise. The switches are sequentially activated by a series of delay elements.

Systems and methods of band amplification with a shared amplifier

Abstract: The present invention provides systems and methods for band amplification with a shared amplifier. In an exemplary embodiment, the wireless band amplification device has with an amplifier with an input port and an output port. The wireless band amplification device also provides two circulators, the first circulator in communication with the input port of the amplifier and the second circulator in communication with the output port of the amplifier. Additionally, two duplexer devices are provided in communication with both circulators. The input port of the amplifier is enabled to receive at least a first frequency band downlink signal and a first frequency band uplink signal. In an alternate embodiment, the input port of the amplifier can be further adapted to receive a second frequency band downlink signal and a second frequency band uplink signal. Additionally, the input port of the amplifier can be further adapted to receive a third frequency band downlink signal and a third frequency band uplink signal.