Showing papers on "Channel length modulation published in 2019"

Electrostatically doped drain junctionless transistor for low-power applications

Abstract: Junctionless transistors (JLT) are a promising alternative to address the stringent junction requirements in conventional transistors. However, JLTs are plagued by high OFF-state leakage current attributed to the band-to-band tunneling at the channel–drain interface. This leakage current is often referred to as gate-induced drain leakage (GIDL). In this paper, we propose an effective technique to suppress GIDL in JLTs. We use the charge plasma concept to realize an electrostatically doped drain (EDD) separated from the channel by an intermediate intrinsic region. Therefore, the proposed EDD–JLT is an n+–n+–i–n+ structure that widens the tunnel barrier at the gate–drain interface in the OFF-state (VGS = 0 V, VDS = 1 V) and offers significant reduction in leakage current. We compare, using 2D TCAD device simulations, the EDD–JLT with the conventional JLT in terms of various digital and analog performance metrics. We observe that EDD–JLTs of gate length 20 nm offer a significant reduction in IOFF (~ 4 orders) while substantially improving ION/IOFF ratio (~ 4 orders) as compared to conventional JLTs. To study the scalability of the proposed technique, the device thickness and gate length were scaled down to 5 nm. We observe that even for scaled-down structure, EDD–JLTs retain their performance benefit. We observe that the analog performance metrics such as intrinsic gain (GmRo), transconductance generation factor (Gm/ID), output conductance (GD), channel length modulation, and drain-induced barrier lowering of EDD–JLTs are also significantly improved as compared to conventional JLTs.

A Non-GCA DG MOSFET Model Continuous into the Velocity Saturation Region

Abstract: Continuous models are developed that go beyond the gradual channel approximation and extend MOSFET ${I}$ – ${V}$ characteristics into the velocity saturation region with finite output conductance. Both the ${n} = {1}$ and ${n} = {2}$ models have been employed. It is shown that the standard relation of channel length modulation for constant mobility must be modified for velocity saturation because the drain current is not simply inversely proportional to the channel length. Regional approximations are applied to derive the explicit expressions for the output conductance in the velocity saturation region in terms of basic device parameters.

Distributed Unique-Size MOS Technique: A Promising Universal Approach Capable of Resolving Circuit Design Bottlenecks of Modern Era

Abstract: In this paper, a new universal technique based on the unique-size MOS transistors is proposed to resolve the analog circuit design bottlenecks imposed by nowadays modern technology downscaling. The method called here “distributed MOS (DMOS) technique” not only permits utilizing minimum-size transistors for analog circuit design, but also paves the way to emerging new generation of modern circuits and systems. It is proved that employing the proposed technique helps the optimum performance of the circuit to be preserved, regardless of minimum-size MOS transistors’ narrow channel effect and channel length modulation. This capability is anticipated to be logically maintained for even smaller transistors offered by future technology. The threshold and early voltage variations versus the MOS transistor channel width and length are investigated by numerical analysis of the data achieved from TSMC library for 180-nm technology using Cadence software, and the result uncertainty ascribed to them exhibited an excellent agreement with the initially developed extended MOS model. Higher linearity with lower THD is interestingly achieved for the new approach. The excellent conformity among the simulation and post-layout results verified the efficiency of the proposed design technique in practical circumstances.

Compact Drain Current Model of Silicon-Nanotubebased Double Gate-All-Around (DGAA) MOSFETs Incorporating Short Channel Effects

Abstract: This paper reports a compact drain current model of silicon nanotube-based double gate all around (DGAA) MOSFET incorporating short channel effects (SCEs). The drain current equation is expressed as a function of charge density, which is derived using the unified surface potential expressions. Fermi-Dirac statistics, the 1-dimensional density of states and Gauss's law have been utilized to develop the analytical expressions of unified surface potentials and charge density. The proposed compact model also takes into account of quantum confinement effects which is significant in devices with the ultra-thin channel region. The SCEs such as velocity saturation effect, threshold voltage roll-off, DIBL, channel length modulation, velocity overshoot, and mobility degradation are well incorporated in the developed model in order to correctly predict the device output and transfer characteristics. Results obtained from the proposed compact drain current model have been validated with TCAD results obtained from the Sentauras device simulator.

Multi-bias Small Signal Circuit Model for FinFET Transistors

Abstract: In this paper, a multi-bias small signal circuit model for Fin Field-Effect transistor (FinFET) is proposed. Channel length modulation effect, non-quasi-static effect and the loss and coupling effects of the substrate are considered in this model. For verification, silicon Multi-Fin MOSFET was fabricated in 14 nm bulk FinFET technology. Based on the improved open/short deembedding method and the proposed model, the scattering parameters calculated by the model are compared with the measurement results. The magnitude root-mean-square-error (RMSE) of scattering parameter is less than 0.0082 for the proposed small signal circuit model. The comparison result indicates that the proposed model achieves high accuracy from 0.2 GHz to 50.2 GHz.

An Improved Surface Potential-Based High-Order Channel Length Modulation Model

Abstract: In this paper, an improved surface-potential-based model is developed. The relationship between gate voltage and surface potential are derived by solving the surface potential equation (SPE). Based on the conventional channel length modulation theory, a modified bias-related high-order channel length modulation coefficient is proposed. The model considers the difference in different channel lengths and the effects of gate voltage on effective channel length, improving the accuracy of the channel length modulation. The sub-threshold region channel current modulation factor is introduced. It improved the weak current characteristics of the subthreshold region effectively. The improved model has been validated for different sizes of transistors fabricated in TSMC 65nm CMOS process. The root-mean-square-error of I-V characters were improved from 0.6083 to 0.2135 in all regions. And in the sub-threshold region, RMSE was improved from $1.068\times 10^{-4}$ to $3.702\times 10^{-5}$ .

Fully differential operational amplifier circuit structure with high linear precision

Abstract: The utility model discloses a fully differential amplifier circuit with high linear precision. The whole circuit mainly comprises an operational amplifier output stage (1), an operational amplifier intermediate stage (2), an operational amplifier output stage (3), a buffer stage (4) and a common-mode feedback stage (5), and belongs to the field of integrated circuits. In order to improve the precision of the circuit, a common-mode feedback stage is added to an operational amplifier to stabilize the output common-mode level, so that the precision of the circuit is improved, and in addition, theinfluence on the output common-mode level caused by the characteristic channel length modulation of a device is improved. In addition, according to the utility model, the cascade mode of two transistors of a cascode current source is improved, the phase margin of the circuit is improved while the circuit precision is ensured, and the stability of the circuit is further improved.

Modeling of Short P-Channel Symmetric Double-Gate MOSFET for Low Power Circuit Simulation

Abstract: In the present era, down scaling of complementary metal-oxide-semiconductor (CMOS) technology has lead the metal-oxide-semiconductor field-effect-transistor's (MOSFET) sizes to nanometer regime which in turn experiencing difficulties due to the effect of physical and technological perspective. Double-gate (DG) MOSFET is considered as a promising device to reduce the shortcoming and shrink down towards nanometer domain. This paper proposes electrostatic potential distribution and drain current models for the lightly doped symmetrical p-channel DG MOSFET. The analytic solution of potential distribution is derived by solving the 2D Poisson's equation incorporated with hole density through the superposition method. The drain current model has been explored by incorporating physical effects like threshold-voltage roll-off, channel length modulation and surface roughness scattering. Functionality of the models has been calculated in MATLAB and the obtained results are verified and compared with state of the art literature.

A fast response charge pump circuit for a phase-locked loop

Abstract: The invention claims a fast response charge pump circuit for a phase-locked loop, comprising a self-biasing cascode bias circuit, a DN differential fractional-mode conversion circuit, a replica circuit, a charge-discharge circuit and a UP differential fractional-mode conversion circuit, wherein the charge-discharge circuit comprises a self-biasing cascode bias circuit, a DN differential fractional-mode conversion circuit and a UP differential fractional-mode conversion circuit A self-biasing cascode bias circuit is used to provide current bias for the core circuit of the charge pump The channel length modulation effect of a single MOS transistor is effectively overcome, and the matching accuracy of the charge current and the discharge current of the charge pump is improved Compared withthe traditional cascode bias circuit, the output voltage swing of the charge pump circuit is improved, and the power supply voltage is reduced The charge/discharge current is supplied by the upper and lower current sources, which restrains the change of charge/discharge current with the output voltage and improves the matching range of charge/discharge current of the charge pump Using the sameswitch tube as the charge pump switch, the inherent mismatch between different switch tubes can be avoided effectively Positive feedback mechanism is adopted to improve the response speed of the switch

Current mirror circuit

Abstract: The invention discloses a current mirror circuit, and belongs to the field of integrated circuits. The current mirror circuit adopts a first PMOS transistor MP1, a second PMOS transistor MP2, a thirdPMOS transistor MP3 and a fourth PMOS transistor MP4 to form a current mirror clamping circuit 300, and combines a matched resistor R1 and a matched resistor R2 to eliminate the error caused by a channel length modulation effect in a mirror MN1 current (namely, an input current I1) of the second PMOS transistor MP2 and third PMOS transistor MP3 and improve the precision of a current mirror. The current mirror circuit solves the problems that the output swing of the current mirror circuit is limited and the static power consumption is increased due to the fact that output impedance of the current mirror is increased by adopting a cascode or gain boosting or other technologies to improve the imaging precision of the current mirror in related technologies, and achieve the effect of improvingthe precision of the current mirror of the current mirror circuit.

Driving thin film transistor and preparation method, array substrate and display device

Abstract: The present invention discloses a driving thin film transistor and a preparation method, an array substrate and a display device. The driving thin film transistor comprises an active layer, a grid insulation layer and a grid. A channel length L in the active layer is in the range of 35 [mu]m to 50 [mu]m. According to the driving thin film transistor and the preparation method, the array substrateand the display device, the channel length is increased via preparation, the channel length modulation effect of the device is weakened, so that the slope of a saturation area of the driving thin filmtransistor is lowered, and the driving capability of the driving thin film transistor is enhanced. After the device is lightened for a long time, the voltage variation range(s) of a source end and adrain end of the driving thin film transistor are reduced, the current rate of an OLED display device is retarded, so that the OLED display device is in a relatively high brightness state for a longertime, and the life of the OLED device is improved.

Study of device parameters for work function engineered gate recessed S/D SOI MOSFET incorporating quantum mechanical effects

Abstract: For the first time analytical modeling of nanoscale work function engineered gate recessed S/D SOI MOSFET including quantum mechanical effects has been presented based on the solution of 1 D Schrodinger and 2 D Poisson’s equation. As classical models are insufficient in nanoscale regime, quantization effect has been incorporated in this model to explore the actual potential profile characteristics along the film thickness. An extensive calculation has been carried out with proper boundary condition to solve the 2-D Poisson’s equation for device parameters. The value of deviated quantum threshold voltage has been calculated from classical model, and then these two are added to resolve the final quantum threshold voltage. Channel length modulation has also been taken into consideration during drain current modeling for this structure. A comparative study based on the threshold voltage, drain current, transconductance and drain conductance has been presented for the classical and quantum model. The results are also compared with the simulation of SILVACO Deck build, Deck Editor Version 4.2.5.R (aka 4.2.5.R) device simulator to validate the proposed model.