Showing papers on "Comparator applications published in 1999"

Realizing analog-to-digital converter on a digital programmable integrated circuit

Abstract: An analog-to-digital converter (ADC) is realized in a field programmable gate array (FPGA) without adding special dedicated analog circuitry. In a digital application, a comparator in an interface cell of the FPGA compares an incoming digital signal to a reference voltage. Adjusting of the reference voltage allows the interface cell to support different digital I/O standards. In one embodiment, the comparator is not used for this digital purpose, but rather is used as a comparator in an ADC. A flash ADC is realized by using the comparators of numerous interface cells as the comparators of the flash ADC. Conversion speed is increased by reducing the impedance of the analog signal input path. An on-chip resistor string is provided so that the flash ADC can be realized without external components. In another embodiment, the comparator of the interface cell is the comparator of a successive approximation ADC. In some embodiments, an interface cell has a pad that is usable for receiving a digital signal or for receiving an analog signal. The interface cell includes special dedicated analog circuitry that has a differential input lead that is programmably couplable to the pad.

Analog driver for led or similar display element

Abstract: The analog driver (10) for a display device which is controlled by current, such as an LED, includes a strobed analog input which charges a storage capacitor (18). The voltage across the storage capacitor (18) is fed to the positive input of a comparator (22). The negative input of the comparator (22) receives the voltage from a feedback resistor (30) which is in series with the drive voltage, the drive FET (28) (with a gate connected to the output of the comparator (22)) and the light emitting device. Additionally, a reset FET (32) is provided in parallel with the storage capacitor (18). Displays can be manufactured by a series of panels, each of the panels including an array of these drivers and light emitting devices, along with appropriate control circuitry.

Wholly integrated switch-on control loop of a high voltage power transistor of a quasi resonant flyback converter

Abstract: A flyback DC--DC converter employs a flyback transformer for storing and transferring energy to a load having an auxiliary winding whose voltage is compared by a comparator with a threshold to detect its crossing. As a consequence, a power transistor driving the primary winding of the transformer is switched on through a control flip-flop, for a new phase of conduction and accumulation of energy, whose duration is established by a secondary control loop of the output voltage producing the switching off of the power transistor for a successive energy transfer phase toward the load of the energy stored in the transformer during the preceding conduction phase. The converter has a wholly integrated control circuit that includes a second comparator of the voltage existing on the current terminal of the power transistor connected to the primary winding of the transformer with respect to the ground potential of the circuit. Furthermore, a delay network is coupled in cascade to the output of a first comparator and has an output coupled to a second input of a logic gate, so that under steady state functioning conditions of the converter, the setting of the flip-flop is done by the second comparator rather than by the first comparator.

Data phase locked loop circuit

Abstract: A phase comparator circuit reducing the effects of offset and jitter, and a data Phase Locked Loop circuit incorporating the phase comparator circuit. The phase comparator circuit includes a Delay Locked Loop circuit for outputting a delay, signal PLDTD with a delay according to an oscillation frequency of a voltage controlled oscillator, with respect to an input data PLDT, a D-type flip-flop for outputting a delay signal PLDTL by latching an input data PLCK according to an oscillation clock PLCK output from a voltage controlled oscillator, and a phase comparator for comparing phases of delay signals PLDTD and PLDTL.

Calibrated quasi-autozeroed comparator systems and methods

Abstract: A multistage comparator is calibrated to remove quasi-autozero voltages derived from the native comparator offset and autozero switch charge injection offsets. A multistage comparator includes a plurality of series connected amplifiers each having a programmable source, and further including a latch. A calibration method for a multistage comparator includes calibrating the first of a series of amplifiers first for both voltage offset and charge injection errors thereby to remove the quasi-autozero voltage and charge injection offsets.

Hysteresis comparator circuit consuming a small current

Abstract: A hysteresis comparator circuit and a waveform generating circuit reduce a power consumption of a DC/DC converter so as to improve a power consumption efficiency when the DC/DC converter is operated with a relatively small load. The hysteresis comparator circuit is connected to a reference voltage source providing a reference voltage. A hysteresis comparator compares an input voltage with one of a first threshold voltage and a second threshold voltage. A hysteresis voltage generating circuit selectively generates one of the first and second threshold voltages by controlling a state of electric charge stored in each of the capacitors. An electric charge stored in the capacitors is provided from the reference voltage source.

Analog/digital converter apparatus

Abstract: An analog/digital converter apparatus includes a reference signal generator circuit for generating a reference signal, a comparator section for determining a relationship in level between an input analog signal and the reference signal, and an encoder for converting a comparison result of the comparator section into a digital signal as an output signal. The comparator section has a comparator for comparing the input analog signal with the reference signal and a switching circuit which is interposed between the comparator and each of an input terminal for the input analog signal and a reference signal output terminal for the reference signal and used for switching the input signal lines of the comparator to compensate an equivalent input offset.

Fully differential interpolating comparator bank and method

Abstract: An interpolating comparator bank having first and second differential amplifiers, each having a differential input and a differential output and first, second and third comparator circuits, each having differential inputs. The differential output of the first differential amplifier and second differential amplifier are coupled to the first and second comparator inputs, respectively. The differential outputs of the first and second differential amplifiers are also both coupled to the differential input of the second comparator circuit. In analog to digital converter circuit applications, the first and second comparators function to provide outputs indicative of the magnitude of a differential input voltage relative to first and third differential reference voltages produced, for example, by a resistor network. The second comparator circuit provides an output indicative of the magnitude of the differential input relative to a second differential input voltage which is not produced by the resistor network but which has a magnitude intermediate that of the first and second differential reference voltages.

Hiccup-mode current protection circuit for switching regulator

Abstract: A hiccup mode current protection circuit for switched mode power converters for high power applications is provided. The circuit features a comparator for comparing an indicating voltage to a reference voltage and outputting a control signal to a disabling input where the indicating voltage exceeds a predetermined voltage threshold. The control signal also causes a switch to reduce the reference voltage to ensure that the comparator continues to output the control signal regardless of a drop in the indicating voltage. The control signal is maintained by a comparator for only a predetermined time period such that the switch eventually returns the reference voltage to its pre-reduction state, allowing the comparator to discontinue outputting the control signal if the indicating voltage is below the predetermined voltage threshold.

Analog-to-digital flash converter for generating a thermometric digital code

Abstract: A flash analog-to-digital converter includes a bank of comparators with a differential output, generating a thermometric code, and a bank of three-input logic NOR gates. The converter has enhanced immunity to noise and reduced imprecisions by providing for a passive interface including a plurality of voltage dividers each connected between the noninverted output of a respective comparator and the inverted output of the comparator of higher order of the bank. A corresponding logic NOR gate of the bank has a first input coupled to the inverted output of the respective comparator, a second input coupled to the noninverted output of the comparator of higher order and a third input coupled to an intermediate node of the voltage divider.

Comparator circuit with built-in hysteresis offset

Abstract: A high-gain comparator has a built-in hysteresis offset voltage generation feature. The comparator is characterized as having several elements, including a differential amplifier pair that is provided with first and second input voltages, an offset voltage element that creates an offset voltage between the first and second elements of the differential amplifier pair, an output generation element operably coupled to the differential amplifier pair that generates an output voltage of the comparator which is indicative of a voltage difference between the first and second input voltages, and a control element operably coupled to the output signal that controllably adjusts the offset voltage from a first state to a second state in accordance with the output signal to create a hysteresis condition of the comparator.

Phase locked loop for generating two disparate, variable frequency signals

Abstract: A method and apparatus for generating two disparate frequency reference signals using a single phase locked loop. The circuit includes a local oscillator for generating a reference signal and a phase comparator for comparing the reference signal with a feedback signal. The output of the phase comparator is converted to a first one of the desired output frequencies by a voltage controlled oscillator. That signal is also fed to a variable frequency divider circuit under control of a Σ/Δ converter which generates a lower frequency signal without creating a secondary frequency tone. The lower frequency signal is the second of the output frequencies. This signal also is fed back to the second input of the phase comparator through a fixed frequency divider.

High accuracy comparator

Abstract: An embodiment of the invention is directed to a metal oxide semiconductor field effect transistor (MOSFET) comparator, which includes a differential amplifier having first and second inputs and first and second outputs. A first offset storage device is connected to the first input at one end and receives a first input signal of the comparator at another end. A second offset storage device is connected to the second input at one end and receives the first input signal during an autozero time interval and a second input signal of the comparator thereafter. During the autozero time interval, offset voltages are stored. Thereafter, the offsets are cancelled when the input signals are applied to their respective storage device. In a particular embodiment of the invention, the amplifier features a dual purpose load that causes the amplifier to first preamplify and then regeneratively drives the outputs.

Method for controlling the output voltage of a DC-DC converter

Abstract: A DC--DC converter includes an offset comparator that compares an output voltage with a reference voltage in parallel with an error amplification circuit, which also compares the output voltage with the reference voltage. The offset comparator has a predetermined offset voltage set between its input terminals so that the offset comparator outputs a high signal when the voltage difference between its inputs exceeds the predetermined level. The output of the offset comparator is input, along with the error amplification circuit output, into a PWM comparator. The signal output by the offset voltage comparator allows the DC--DC converter to more quickly respond to a sudden increase in current consumption by a connected load. In responding to the increased current draw, the DC--DC converter quickly converges back at the reference voltage, such that the DC--DC converter provides a very stable output voltage.

Feedback charge-transfer comparator with zero static power

Abstract: The feedback charge transfer (FCT) amplifier latch comparator uses a dynamic feedback mechanism in the charge transfer (CT) preamplifier. The FCT amplifier latch rapidly amplifies input signal and latches with zero static power. Circuit operation is nearly insensitive to device parameter fluctuations. The authors present the design and performance characteristics of such a comparator implemented in a 1.2 /spl mu/m double-poly double metal CMOS process.

A CMOS Voltage Comparator with Rail-to-Rail Input-Range

Abstract: A simple new continuous-time CMOS comparator circuit with rail-to-rail input common-mode range and rail-to-rail output is presented. This design uses parallel complementary decision paths to accommodate power-supply-valued inputs. The 2 decision results are combined at a current summing node, converted to a voltage, and buffered to drive voltage loads. The circuit has been realized in an area of 416 μm×221 μm in a MOSIS 2-micron CMOS technology. Average delay of about 63 ns has been measured at 3 V (1.3 mA), and about 89 ns at 5 V (1.1 mA).

A 2.5-V BiCMOS comparator with current-mode interpolation

Abstract: A high-speed latched comparator based on a current-mode architecture is presented. It achieves a sampling speed of 150 MS/s at 2.5 V supply, with a power consumption lower than conventional schemes. Its very low kickback noise makes it especially suitable for differential analog-to-digital converters (ADCs). Moreover, it supports precise 2X interpolation in current mode at full clock speed, allowing a further reduction of the ADC power consumption. The comparator was implemented in a 0.8 /spl mu/m BiCMOS technology.

Differential comparator with stable switching threshold

Abstract: A differential threshold comparator is provided which includes an input stage and a threshold stage, both supplied with current by a common current mirror. Both stages are differential comparators, with the input stage having terminals for receiving an input signal and the threshold stage having terminals for receiving a threshold voltage. The threshold comparator produces a signal which indicates whether the difference between input signal voltages exceeds the threshold voltage.

Low-current oscillator with hysteresis input buffer

Abstract: A low-current oscillator with input buffer hysteresis for increased noise immunity during oscillator start-up. Resistors are switched in and out of the comparator input elements creating offsets in one leg of the comparator at a time.

Comparator with dynamic hysteresis

Abstract: A comparator is presented which is based on the use of a time domain phenomenon called 'dynamic hysteresis'. This comparator features only one threshold and a short-time controllable noise immunity.

Low power differential comparator with stable hysteresis

Abstract: A low power differential comparator wherein the input stage bias is used not only to set a bias level but is also used to set the hysteresis level of the differential comparator circuit. The positive and/or negative inputs to the differential comparator circuit are referred to ground to reduce the total DC current draw, e.g., by a factor of 7. The multiple use of the input stage bias and grounded connections to the positive and/or negative inputs reduce the overall current requirements of the differential comparator circuit substantially while maintaining full operating speed as compared to conventional differential comparator circuits. In one embodiment using the low power differential comparator circuit, a clock receiver implements hysteresis which is relatively independent from variations in environmental factors such as temperature, and from power supply variations. In this embodiment, the input stage of a low power comparator circuit is biased by the output of a bias circuit. The bias circuit, which in the disclosed embodiment is a regulated current source, may be started-up with the output of a start-up circuit if desired. In operation, when the temperature increases the bias current decreases, but the values of hysteresis resistors in the low voltage comparator also increase. Therefore, the resultant hysteresis value does not change appreciably.

High voltage comparator

Abstract: A high voltage comparator circuit quickly identifies the voltage level of the predetermined voltages required for program operations. Through the series of transistors, the precise timing of when the predetermined voltages are at their operating voltage level is identified.

Voltage drop circuit

Abstract: A voltage drop circuit includes a comparator for comparing a predetermined reference voltage and a generated internal voltage, a first current supply unit for being activated in accordance with an output of the comparator, a level converter for converting the output of the comparator to a CMOS level, a second current supply unit for being activated in accordance with an output of the level converter, and a load circuit for receiving current from the first and second current supply units and forming an internal voltage.

Dc/dc converter for suppressing effects of spike noise

Abstract: A comparator 5 changes an output signal from [H] to [L] when a voltage drop VR occurring at a current sensing resistance Rsens becomes greater than a reference voltage VS by a current IL. When the output signal of the comparator 5 is [H], a control circuit 1 outputs a control signal of a duty ratio responsive to the voltage deviation signal outputted from a differential amplification circuit 4 to a switching element 2 . When the output signal of the comparator 5 is [L], the control circuit 1 outputs a control signal, which turns off the switching element 2 , to the switching element 2 . When the switching element 2 is switched, the control circuit 1 connects a filter F of a large time constant to the input side of the comparator 5 by switching off a switching element Tr 1 in a predetermined period of time.

Offsetting comparator device and comparator circuit

Abstract: An offsetting comparator device includes master and slave comparator circuits and a reference differential voltage generator. The master comparator circuit supplies a sensed current corresponding to a potential difference represented by a differential signal on a transmission line. The reference differential voltage generator generates a reference differential voltage based on an intermediate potential of the differential signal. And the slave comparator circuit supplies a current corresponding to the potential difference as offset current. The offsetting comparator device outputs a differential current between the sensed and offset currents and therefore shows an offset in its input/output characteristics. The master and slave comparator circuits have the same circuit configuration. Thus, if the characteristic of the sensed current output from the master comparator circuit has changed due to a potential level variation of the differential signal, then the characteristic of the offset current also changes similarly. Thus, the offsetting comparator device can obtain a constant offset voltage even if the potential level of the differential signal has changed.

Arrangement for phase matching of data signal to clock signal in digital integrated circuit, e.g. for mobile telephones and software radio

Abstract: The arrangement has an adaptive delay stage (D) for delaying the data signal w.r.t. the clock signal, at least three bistable flip-flop stages (FF1-FF3), a first comparator stage (XOR1) connected to the outputs of the first and second bistable stages, a second comparator stage (XOR2) connected to the outputs of the second and third bistable stages and a control stage (C) connected after the comparator stages. The control stage evaluates the comparator output signals and controls the data signal delay. The first, second and third bistable stage data inputs are respectively the delayed data signal, the data signal delayed by a second delay element (T2) and the data signal delayed by a further second delay element (T2); their clock inputs all receive the clock signal.

Time characteristics of a Josephson-balanced comparator

Abstract: We consider the time characteristics of a balanced comparator formed by two Josephson junctions connected in series. Such a decision-making junction pair is an essential component of all RSFQ cells. The analysis is performed within the framework of a simple time-dependent oscillator model. Turn-on delay and uncertainty (jitter) of comparator switching times are analysed taking into account the influence of thermal fluctuations and the finite time duration of clock pulse. Restrictions on speed performance of RSFQ cells caused by both times are considered. Some practical recommendations on the clock frequency increase are also discussed.

Sense amplifier/comparator circuit and data comparison method

Abstract: A comparator circuit (40) includes a comparator network and a comparator enabling device (80) and may be integrated with a sense amplifier circuit (41). The comparator network is adapted to receive a complementary pair of reference data signals (B, B13) and a complementary pair of analog data signals (d1, d1b). An output of the comparator circuit (40) represents a comparison of the data represented by the reference data signals and the data represented by the analog data signals. The comparator output is generated in response to a comparator enable signal (SE) applied to the comparator enabling device (80) while the input data is applied to the comparator network. The comparator enable signal (SE) is applied at a time when the analog data signals (d1, d1b) have developed a minimum differential level.

Latching comparator utilizing resonant tunneling diodes and associated method

Abstract: A latching comparator and associated method are disclosed that utilize resonant tunneling diodes, or other two-terminal devices possessing regions of negative differential operating resistance in their current-voltage characteristics, and Schottky diodes to provide high speed and reliable analog to digital conversions. In one embodiment, the latching comparator includes a differential amplifier, resonant tunneling diodes, and cross-coupled resistors. The latching comparator may include mode selection circuitry having a track mode signal and a latch mode signal as inputs. In addition, the latching comparator may include a plurality of Schottky diodes connected in series with the resonant tunneling diodes and the cross-coupled resistors.

Sense amplifier with extended supply voltage range

Abstract: A sense amplifier for a memory includes a comparator and a bit line polarization circuit. The comparator receives a first signal representative of a current flowing through a memory cell and a second signal representative of a reference current. Additionally, the comparator includes a stage in a common source configuration and an active load for the stage, and the bit line polarization circuit provides a polarization voltage level that is independent of the supply voltage level. In a preferred embodiment, the sense amplifier also includes an output stage that improves switching time at high supply voltages.