Showing papers on "Core router published in 2017"

An Efficient Network-on-Chip Router for Dataflow Architecture

Abstract: Dataflow architecture has shown its advantages in many high-performance computing cases. In dataflow computing, a large amount of data are frequently transferred among processing elements through the network-on-chip (NoC). Thus the router design has a significant impact on the performance of dataflow architecture. Common routers are designed for control-flow multi-core architecture and we find they are not suitable for dataflow architecture. In this work, we analyze and extract the features of data transfers in NoCs of dataflow architecture: multiple destinations, high injection rate, and performance sensitive to delay. Based on the three features, we propose a novel and efficient NoC router for dataflow architecture. The proposed router supports multi-destination; thus it can transfer data with multiple destinations in a single transfer. Moreover, the router adopts output buffer to maximize throughput and adopts non-flit packets to minimize transfer delay. Experimental results show that the proposed router can improve the performance of dataflow architecture by 3.6x over a state-of-the-art router.

The Impact of Router Outages on the AS-level Internet

Abstract: We propose and evaluate a new metric for understanding the dependence of the AS-level Internet on individual routers. Whereas prior work uses large volumes of reachability probes to infer outages, we design an efficient active probing technique that directly and unambiguously reveals router restarts. We use our technique to survey 149,560 routers across the Internet for 2.5 years. 59,175 of the surveyed routers (40%) experience at least one reboot, and we quantify the resulting impact of each router outage on global IPv4 and IPv6 BGP reachability.Our technique complements existing data and control plane outage analysis methods by providing a causal link from BGP reachability failures to the responsible router(s) and multi-homing configurations. While we found the Internet core to be largely robust, we identified specific routers that were single points of failure for the prefixes they advertised. In total, 2,385 routers -- 4.0% of the routers that restarted over the course of 2.5 years of probing -- were single points of failure for 3,396 IPv6 prefixes announced by 1,708 ASes. We inferred 59% of these routers were the customer-edge border router. 2,374 (70%) of the withdrawn prefixes were not covered by a less specific prefix, so 1,726 routers (2.9%) of those that restarted were single points of failure for at least one network. However, a covering route did not imply reachability during a router outage, as no previously-responsive address in a withdrawn more specific prefix responded during a one-week sample. We validate our reboot and single point of failure inference techniques with four networks, finding no false positive or false negative reboots, but find some false negatives in our single point of failure inferences.

Design of software router with a modular structure and automatic deployment at virtual nodes

Abstract: In this work we describe the process of deploying virtual routers in accordance with flexible time allocation of virtual access to the processor. We developed the model of software router with a set of modern mechanisms and algorithms service information flows. Using the model of the router we enhanced functionality of the device: added mode of deployment of virtual nodes with the possibility of flexible management of the structural parameters. Usign the developed software router model, we conducted the research of service quality of IPTV traffic through deployment of virtual devices for processing traffic of different service classs.

An asynchronous NoC router in a 14nm FinFET library: Comparison to an industrial synchronous counterpart

Abstract: An asynchronous high-performance low-power 5-port network-on-chip (NoC) router is introduced. The proposed router integrates low-latency input buffers using a circular FIFO design, and a novel end-to-end credit-based virtual channel (VC) flow control for a replicated switch architecture. This asynchronous router is then compared to an AMD synchronous router, in a realistic advanced 14nm FinFET library. This is the first such comparison, to the best of our knowledge, using a real synchronous router baseline already fabricated in several commercial products. Initial post-synthesis pre-layout experiments show dominating results for the asynchronous router, when compared to the synchronous router. In particular, 55% less area and 28% latency improvement are observed for the asynchronous implementation. Also, 88% and 58% savings in idle and active power, respectively, are obtained.

Extending the performance of hybrid NoCs beyond the limitations of network heterogeneity

Abstract: To meet the performance and scalability demands of the fast-paced technological growth towards exascale and big data processing with the performance bottleneck of conventional metal-based interconnects (wireline), alternative interconnect fabrics, such as inhomogeneous three-dimensional integrated network-on-chip (3D NoC) and hybrid wired-wireless network-on-chip (WiNoC), have emanated as a cost-effective solution for emerging system-on-chip (SoC) design. However, these interconnects trade off optimized performance for cost by restricting the number of area and power hungry 3D routers and wireless nodes. Moreover, the non-uniform distributed traffic in a chip multiprocessor (CMP) demands an on-chip communication infrastructure that can avoid congestion under high traffic conditions while possessing minimal pipeline delay at low-load conditions. To this end, in this paper, we propose a low-latency adaptive router with a low-complexity single-cycle bypassing mechanism to alleviate the performance degradation due to the slow 2D routers in such emerging hybrid NoCs. The proposed router transmits a flit using dimension-ordered routing (DoR) in the bypass datapath at low-loads. When the output port required for intra-dimension bypassing is not available, the packet is routed adaptively to avoid congestion. The router also has a simplified virtual channel allocation (VA) scheme that yields a non-speculative low-latency pipeline. By combining the low-complexity bypassing technique with adaptive routing, the proposed router is able to balance the traffic in hybrid NoCs to achieve low-latency communication under various traffic loads. Simulation shows that the proposed router can reduce applications’ execution time by an average of 16.9% compared to low-latency routers, such as SWIFT. By reducing the latency between 2D routers (or wired nodes) and 3D routers (or wireless nodes), the proposed router can improve the performance efficiency in terms of average packet delay by an average of 45 % (or 50 % ) in 3D NoCs (or WiNoCs).

Changepoint-based anomaly detection in a core router system

Abstract: Prognostic diagnosis is desirable for commercial core router systems to ensure early failure prediction and fast error recovery. The effectiveness of prognostic diagnosis depends on whether anomalies can be accurately detected before a failure occurs. However, traditional anomaly detection techniques fail to detect “outliers” when the statistical properties of the monitored data change significantly as time proceeds. We describe the design of a changepoint-based anomaly detector that first detects changepoints from collected time-series data, and then utilizes these changepoints to detect anomalies. Two approaches based on maximum-likelihood estimation are implemented to detect different types of changepoints. A clustering method is then developed to identify a wide range of normal/abnormal patterns from changepoint windows. Data collected from a set of commercial core router systems are used to validate the proposed anomaly detector. Experimental results show that our changepoint-based anomaly detector achieves better performance than traditional methods.

Distributed and Dynamic Shared-Buffer Router for High-Performance Interconnect

Abstract: Most Network-on-Chip routers dedicate a set of buffers to the input and/or output ports. This design decision leads to buffer underuti-lization especially when running applications with non-uniform traffic patterns. In order to maximize resource usage for performance and energy gains, we present a synchronous and elastic buffer implementation of a router architecture called Roundabout with intrinsic resource sharing. Roundabout is inspired by real-life traffic roundabouts and consists of lanes shared by multiple input and output ports. Roundabout offers performance improvement of 61% for uniform traffic pattern and up to 88% for non-uniform traffic pattern over the Hermes router, a typical input buffered router. In terms of power, it consumes 24% less than the Hermes router. Roundabout provides a highly parametric architecture that can produce different router configurations with varying topological trade-offs for performance gains without sacrificing area.

Scalable and Power-Efficient Implementation of an Asynchronous Router with Buffer Sharing

Abstract: Network-on-Chip provides scalable communication in Systems-on-Chip with many Intellectual Property cores Studies have shown that unutilized router buffers lead to significant network performance degradation This work presents Roundabout, a new asynchronous router architecture with inherent and effective buffer utilization Inspired by real-life multi-lane roundabouts, it consists of lanes shared by input and output ports A prototype of Roundabout is evaluated using 45nm CMOS technology The router is able to achieve a throughput of 465 Mflit/sec It achieves a network saturation threshold of 129 Gbps on a 4x4 Mesh topology network Roundabout performance, area and power results are competitive with existing synchronous and asynchronous solutions It provides good topological tradeoffs for significantly improving network performance without corresponding area overhead

Wireless fidelity connection method and system for intelligent terminal and router

Abstract: An embodiment of the present disclosure discloses a wireless fidelity connection method and a wireless fidelity connection system for an intelligent terminal and a router, wherein the method comprises the following steps: the intelligent terminal monitors a Wi-Fi beacon frame or a Wi-Fi probe response frame which is sent from the router, and determines whether an identification field is carried in the Wi-Fi beacon frame or the Wi-Fi probe response frame; if yes, the intelligent terminal determines whether content of the identification field is identical to content of a preset identification; and if yes, the intelligent terminal employs a Wi-Fi password which is preset in the intelligent terminal to connect the router so as to establish a Wi-Fi connection between the intelligent terminal and the router. The workload of establishing the Wi-Fi connection between the intelligent terminal and the router is reduced, and efficiency of the Wi-Fi connection is increased.

Distributed stateless inference of hop-wise delays and round-trip time for internet protocol traffic

Abstract: In an embodiment, a computer implemented method for determining network delay values comprises receiving, by a management server that is communicatively coupled via one or more networks or internetworks to a first router and a second router, two or more first timestamp values from the first router at first times at which two or more packets associated with a particular packet flow are received at the first router; receiving by the management server two or more second timestamp values from the second router at second times at which the same two or more packets associated with the same particular packet flow are received at the second router; determining one or more of: a one-way delay time in which the particular packet flow travels between the first router and the second router based on the first timestamp values and the second timestamp values; an inferred round-trip time.

Symbol-based health-status analysis in a core router system

Abstract: To ensure high reliability and rapid error recovery in commercial core router systems, a health-status analyzer is essential to monitor the different features of core routers. However, traditional health analyzers need to store a large amount of historical data in order to identify health status. The storage requirement becomes prohibitively high when we attempt to carry out long-term health-status analysis for a large number of core routers. We describe the design of a symbol-based health status analyzer that first encodes, as a symbol sequence, the long-term complex time series collected from a number of core routers, and then utilizes the symbol sequence to do health analysis. The symbolic aggregation approximation (SAX) and moving-average-based trend approximation methods are implemented to encode complex time series in a hierarchical way. Hierarchical agglomerative clustering and sequitur rule discovery are implemented to learn important global and local patterns. Two classification methods are then utilized to identify the health status of core routers. Data collected from a set of commercial core router systems are used to validate the proposed health-status analyzer. The experimental results show that our symbol-based health status analyzer requires much lower storage than traditional methods, but can still maintain comparable diagnosis accuracy.

Configuring Linux System for Internet Protocol based Multimedia Communication Network

Abstract: This research paper is trying to implement an idea through which we can configure a system have an effective multimedia communication network through a Linux based router with internet protocol. Which deals with the protocol used in the past IPv4 and presently used IPv6. It states about the use IPv4 in IPv6 Networks and different combinations of IP networks, the cost effective design is the use of IPv4 server and IPv6 client. The objective of this research extends to set up a network lab and Configuring Linux system as router, also to have a study of performance and to examine the analysis of multimedia communication in various topologies using internet protocol networks. There are 4 computers used to configure the network of multimedia communication host a and host b serves as the server and client and the other 2 computers are configured to act as routers, ie., router 1 & router 2. Method: Connections are done by using Ethernet and optical fiber cables, by creating a virtual server with connection oriented network of TCP (Transmission Control Protocol), also measuring the performance of the internet protocol between the intermediate routers. The routers are configured as Dual Stack Protocol by the method of Tyga Tunneling process. Findings: Finally, this research eliminates the use of routers and switches in a computer network, Increase in Efficiency, Throughput & QOS of multimedia data transmission by using OFC also decrease in Delay & Data loss by replacing Ethernet by OFC.

On Bit-Serial NoCs for FPGAs

Abstract: We can build lightweight bit-serial FPGA NoC routers thatcost 20 LUT, 17 FF per router and operate at 800–900 MHzspeeds. Each bit-serial router implements deflection-routing on aunidirectional torus topology requiring 1b-wide connection perport. The key ideas that enable this implementation are (1)reformulation of the dimension-ordered routing (DOR) functionusing compact 1 LUT, 1 FF streaming pattern matchers, (2)compact retiming of the datapath signals into SRL16 blocks, and(3) careful FPGA layout to efficiently pack the router logic intosmall rectangular regions 2×4 SLICEs on the chip. We anticipatethese bit-serial NoCs can be used in a variety of scenariosincluding overlay support for triggered debug, lightweight controlsignal dissemination, massively-parallel bit-serial processing.

A Multi-stage IPv6 Routing Lookup Algorithm Based on Hash Table and Multibit Trie

Abstract: The address length of IPv6 is 128 and it has no classification addressing, which makes routing lookup processing burden of core router is heavier and the requirements are higher. As many existing algorithms cannot adapt to new requirements after expanding to IPv6, it is necessary to propose a new routing lookup algorithm based on IPv6. After thorough analysis of the IPv6 address prefix distribution regularity, this paper proposes a new scheme based on simple data structure: Hash Table and Multibit Trie (retrieval). This algorithm first classifies the prefix value and then starts its first lookup by using the first 48bits prefix of the IPv6 Address. Simulation results show that in most cases, the algorithm needs only one memory access to find the next hop routing information. This algorithm has high lookup speed and can be easily implemented with hardware.

Design of Efficient Pipelined Router Architecture for 3D Network on Chip

Abstract: As a relevant communication structure for integrated circuits, Network-on-Chip (NoC) architecture has attracted a range of research topics. Compared to conventional bus technology, NoC provides higher scalability and enhances the system performance for future System-on-Chip (SoC). Divergently, we presented the packet-switching router design for 2D NoC which supports 2D mesh topology. Despite the offered benefits compared to conventional bus technology, NoC architecture faces some limitations such as high cost communication, high power consumption and inefficient router pipeline usage. One of the proposed solutions is 3D design. In this context, we suggest router architecture for 3D mesh NoC, a natural extension of our prior 2D router design. The proposal uses the wormhole switching and employs the turn mod negative-first routing algorithm Thus, deadlocks are avoided and dynamic arbiter are implemented to deal with the Quality of Service (QoS) expected by the network. We also adduce an optimization technique for the router pipeline stages. We prototyped the proposal on FPGA and synthesized under Synopsys tool using the 28 nm technology. Results are delivered and compared with other famous works in terms of maximal clock frequency, area, power consumption and estimated peak performance.

Application deployment system and method

Abstract: PROBLEM TO BE SOLVED: To provide a system and a method capable of deploying the application of a service provider in the best place, in a network environment where data centers are distributed in a carrier network.SOLUTION: An application deployment system includes a facility management information storage unit 440 for storing the delay time information of a path and the path length information, respectively, of a section from the connection point of an end user terminal and a carrier network 100 to an edge router 110, a section from the edge router 110 to a core router 120, and a section from the core router 120 to the connection point of the carrier network 100 and an external network, and a deployment determination unit 410 for determining in which data center 111 each application 310 is deployed, based on the inputted service requirement and the information stored in the facility information storage means 440.SELECTED DRAWING: Figure 4

System and method for supporting router SMA abstractions for SMP connectivity checks across virtual router ports in a high performance computing environment

Abstract: Systems and methods for supporting SMP connectivity checks across virtual router in a high performance computing environment. In accordance with an embodiment, SMA model enhancements allow for the possibility to send a packet (i.e., SMP) that is addressed to a local router port. The SMA where the packet is addressed can receive the packet, and then apply a new attribute that defines that the requested information is on a remote node (e.g., connected by a physical link across subnets). In accordance with an embodiment, the SMA can operate as a proxy (receives a SMP and sends another request), or the SMA can modify the original packet and send it on as an inter-subnet packet.

Deployment method and device for communication network

Abstract: The invention discloses a deployment method and device for a communication network. The method comprises the following steps: performing cross-domain connection on routers within multiple domain ranges, wherein the cross-domain connection is used for representing communication of router equipment within the multiple domain ranges; connecting the routers within the multiple domain ranges into core router equipment; cutting over the router equipment connected into the core router equipment. According to the deployment method disclosed by the invention, the technical problems of low system capacity and relatively low operation quality of a network architecture of most companies in the prior art are solved.

Guide to Cisco Routers Configuration: Becoming a Router Geek

Abstract: This work provides a guide to the configuration of Cisco routers, from tasks for beginners to advanced operations. A collection of detailed "how-to" instructions are presented, which will be of use to all professionals and students who engage with Cisco routers in the field or in the lab. The guide starts with the simple step-by-step task of connecting the router and performing basic configuration, before building up to complex and sensitive operations such as router IOS upgrade and Site-to-Site VPNs.

A Design for an Internet Router with a Digital Optical Data Plane

Abstract: This paper presents a complete design for an optical Internet router based on the component steps required for Internet protocol (IP) packet forwarding. Implementations of hop count decrement and header matching are integrated with a simulation-based approach to variable-length packet traffic merging that avoids recirculation, demonstrating an approach for an all-optical data plane. A method for IPv4 checksum computation is introduced, and this and previously designed components are extended from binary to higher-density (multiple bits per symbol) encodings. The implications of this design are considered, including the potential for chip-level and system integration, as well as the requirements of basic optical processing components.

Metropolitan area network system

Abstract: An embodiment of the present invention provides a metropolitan area network system, relating to the technical field of communication. The metropolitan area network system can help improve service deployment efficiency and reduce the construction cost of network capacity expansion. The metropolitan area network comprises customer premise equipment (CPE), an optical access network connected with the CPE, at least one first white box switch connected with the optical access network, an internet data center (IDC) and a core router (CR) that are connected with the at least one first white box switch. The IDC comprises a software defined network (SDN) controller and multiple virtualized network functions (VNF). The CPE supports an OpenFlow protocol and is used for forwarding data between a user terminal and the optical access network under the control of the SDN controller. The at least one first white box switch is used for completing data forwarding among the IDC, the optical access network and the CR under the control of the SDN controller. The optical access network is used for accessing data of a user service to an optical network to transmit. The CR is used for forwarding the received data.

Secured Hash Based Burst Header Authentication Design for Optical Burst Switched Networks

Abstract: Abstract The optical burst switching (OBS) is a promising technology that could meet the fast growing network demand. They are featured with the ability to meet the bandwidth requirement of applications that demand intensive bandwidth. OBS proves to be a satisfactory technology to tackle the huge bandwidth constraints, but suffers from security vulnerabilities. The objective of this proposed work is to design a faster and efficient burst header authentication algorithm for core nodes. There are two important key features in this work, viz., header encryption and authentication. Since the burst header is an important in optical burst switched network, it has to be encrypted; otherwise it is be prone to attack. The proposed MD5&RC4-4S based burst header authentication algorithm runs 20.75 ns faster than the conventional algorithms. The modification suggested in the proposed RC4-4S algorithm gives a better security and solves the correlation problems between the publicly known outputs during key generation phase. The modified MD5 recommended in this work provides 7.81 % better avalanche effect than the conventional algorithm. The device utilization result also shows the suitability of the proposed algorithm for header authentication in real time applications.

Performance Evaluation of Buffer Size for Access Networks in First Generation Optical Networks

Abstract: Enhancing network performance and reducing energy consumption by the routers are two very important design challenges faced by router manufacturers today. Routers require buffers to hold packets in times of delay. Therefore, buffer size plays a big role in router design. Network performance and router energy consumption is determined by the technologies employed to build the routers. Manufacturers use the rule of thumb to assign network buffer to routers, which increases buffer size linearly with an increase in network capacity. This results in large buffers that require a lot of power and board space, and are a challenge to router manufactures. In this paper, we use OPNET simulations to study buffer size in access networks, independent of network capacity, to come up with an optimal buffer size for the network. We propose and use a model to illustrate buffer size that is optimal for access networks. By having a buffer size that can hold at least fourteen packets, we illustrate that this results in reduced power consumption by the router and enhanced network performance.

Virtual Router Redundancy Protocol Fault Detection Method and Routing Device

Abstract: A VRRP fault detection method is applied to a VRRP group including one primary router and one or more secondary routers. The method includes: sending, by the primary router and the secondary router, link detection packets having an echo response function, where a destination address of the link detection packet is a virtual address of the VRRP group. The method also includes determining, by the primary router and the secondary router, whether response packets corresponding to the link detection packets sent by the primary router and the secondary router are received within a predetermined time, and if the primary router and/or the secondary router does not receive the response packet within the predetermined time, determining that the primary router is faulty.

A comparative study of input port and crossbar configurations in NoC router microarchitectures

Abstract: Network-on-Chip (NoC) has emerged as a promising solution as an on-chip interconnect for multi-cores. Most of the research in NoCs revolves around router microarchitecture for power efficiency and performance and in algorithms for efficient data transfer. While many works in the literature discuss the impact of buffer organization on the performance in terms of latency, in this work we evaluate the impact of buffer organization with area and power consumption in the router. In this experimental study, we implement 36 different router architectures with different flit sizes, input port and crossbar configurations. All these router architectures are implemented, synthesized and validated on the 28nm Xilinx Kintex KC705 FPGA hardware for comparison. We have also synthesized these routers using the 1P8M UMC65nm standard cell technology on Cadence ASIC flow. We report that for the same number of buffers, the dynamic power and area can vary by up to 67% based on the configuration. We also find that increasing the number of buffers does not increase area and power by the same proportion. Further we report that the crossbar configuration can be significantly improved by designing routing specific crossbars.

Network management device and network management program

Abstract: PROBLEM TO BE SOLVED: To reduce the maintenance cost of a network, and also to quickly and efficiently provide a user with a network service.SOLUTION: A network management device M comprises: an infrastructure manager unit 2 which manages an IA server, a VM (virtual server), and a core NW-side device (core router and the like) arranged on a core NW, and an access NW-side device (L2SW and the like) arranged on an access NW; and an orchestrator unit 1 which acquires an NS (Network Service) generation request from a host device U. The orchestrator unit generates a VM on which an NW function (APL) operates on the basis of an NS generation request, sets connection points in the NW function, the IA server on which the generated VM operates, the core NW-side device, and the access NW-side device, and generates an NS slice over the core NW and the access NW by connecting the connection points by a link.SELECTED DRAWING: Figure 1

MINOS: regulating router dataplane actions in dynamic runtime environments

Abstract: Programmable routers are emerging as a promising alternative which facilitates the deployment of new network technologies, for example, software-defined networking; meanwhile, theirs programmability and openness also bring risks of security vulnerabilities. Prior work has concentrated on code security and encryption to improve router action honesty. In this paper, we exploit the feasibility of regulating actions on run-time dataplanes by detecting unexpected packet processing operations, which finally provides an honest and backdoor-proof router to operators. The main challenge is to monitor and regulate the action of router dataplane in dynamic runtime environment. Hence we propose Minos, a framework to regulate router actions on dataplanes. Minos takes Action Identifier (AID) as input to perform lookups in a pre-defined white list called Regulated Action Table (RAT), and it finally verifies that the action is (ab)normal. In the end, Minos achieves a pair of irreconcilable goals for security, i.e., costs and effectiveness. We implement and evaluate Minos on Click and DPDK, separately. And our evaluation results show that Minos captures mal-actions with 2 mega-byte spatial costs and no more than 9% performance loss in both Click and DPDK.

FASHION: Fault-Aware Self-Healing Intelligent On-chip Network.

Abstract: To avoid packet loss and deadlock scenarios that arise due to faults or power gating in multicore and many-core systems, the network-on-chip needs to possess resilient communication and load-balancing properties. In this work, we introduce the Fashion router, a self-monitoring and self-reconfiguring design that allows for the on-chip network to dynamically adapt to component failures. First, we introduce a distributed intelligence unit, called Self-Awareness Module (SAM), which allows the router to detect permanent component failures and build a network connectivity map. Using local information, SAM adapts to faults, guarantees connectivity and deadlock-free routing inside the maximal connected subgraph and keeps routing tables up-to-date. Next, to reconfigure network links or virtual channels around faulty/power-gated components, we add bidirectional link and unified virtual channel structure features to the Fashion router. This version of the router, named Ex-Fashion, further mitigates the negative system performance impacts, leads to larger maximal connected subgraph and sustains a relatively high degree of fault-tolerance. To support the router, we develop a fault diagnosis and recovery algorithm executed by the Built-In Self-Test, self-monitoring, and self-reconfiguration units at runtime to provide fault-tolerant system functionalities. The Fashion router places no restriction on topology, position or number of faults. It drops 54.3-55.4% fewer nodes for same number of faults (between 30 and 60 faults) in an 8x8 2D-mesh over other state-of-the-art solutions. It is scalable and efficient. The area overheads are 2.311% and 2.659% when implemented in 8x8 and 16x16 2D-meshes using the TSMC 65nm library at 1.38GHz clock frequency.

Integration of Software Router with Wi-Fi for Enhanced Security

Abstract: The era of networking has moved from dedicated physical network devices to the abstraction of functional software component of those network devices. The functional software component can be run as a software image on any hardware platform. Routers are vital components in any networking environment which routes the information to different networks spread over a geographical area. VyOS is a software router developed by Vyatta, which provides the functionality of a router on generic hardware platform. It is identified that the Wi-Fi module is not integrated with Vyatta software router. Also, websites which use secured protocols, such as hypertext transfer protocol with security (HTTPS), are allowed by default. In this paper, these issues are identified and a suitable driver for Wi-Fi module is developed and implemented. Also, a control mechanism for secured protocols, to allow or block access to the website, is developed and implemented. Test cases are developed to block and allow specific websites. Results show that the websites are blocked successfully and the integration of the Wi-Fi module with the Vyatta software router functioned as expected.