Showing papers on "Depletion region published in 2001"

Spin injection through the depletion layer: A theory of spin-polarized p-n junctions and solar cells

Abstract: A drift-diffusion model for spin-charge transport in spin-polarized p-n junctions is developed and solved numerically for a realistic set of material parameters based on GaAs. It is demonstrated that spin polarization can be injected through the depletion layer by both minority and majority carriers, making all semiconductor devices such as spin-polarized solar cells and bipolar transistors feasible. Spin-polarized p-n junctions allow for spin-polarized current generation, spin amplification, voltage control of spin polarization, and a significant extension of spin diffusion range.

Origin of magnetic field enhancement in the generation of terahertz radiation from semiconductor surfaces

Abstract: We present a theory of the magnetic field enhancement of terahertz (THz) emission from photogenerated carriers in the surface depletion region of a semiconductor. A combination of the Drude-Lorentz model for the carrier dynamics with an appropriate solution of the radiation problem is sufficient to explain the strong B -field enhancement in THz radiation that has been observed experimentally. The effect arises primarily from the increased radiation efficiency of transient currents flowing in the plane of the surface. The model provides quantitative agreement with experiment for the pronounced angular dependence of the enhancement and predicts the correct trend for the enhancement in a variety of materials.

Field effect transistor

Abstract: A field effect transistor with a high withstand voltage and a low resistance is provided. A ring-shaped channel region is disposed inside a source region formed in a ring, and the inside of the channel region is taken as a drain region. A depletion layer extends toward the inside of the drain region, resulting in a high withstand voltage. In the portion, except the portion within a prescribed distance from the corner portion of the channel region, a low resistance conductive layer is disposed, thereby resulting in high withstand voltage.

Additional n-type LDD/pocket implant for improving short-channel NMOS ESD robustness

Abstract: A short-channel NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a channel stop region, has a n-source and a n-drain, each comprising a shallow region extending to the transistor gate and a deeper region recessed from the gate, and both having a depletion region when reverse biased. The shallow regions are surrounded in part by an enhanced p-doping implant pocket. The transistor further has in these regions of enhanced p-doping another region of a p-resistivity higher than the remainder of the semiconductor. These regions extend laterally approximately from the inner border of the respective shallow region to the inner border of the respective recessed region, and vertically from a depth just below the depletion regions of source and drain to approximately the top of the channel stop regions. According to the invention, these regions of higher p-type resistivity are created after gate definition by an ion implant of compensating n-doping, such as arsenic or phosphorus, using the same photomask already used for implants creating the extended source and drain and the pockets of enhanced p-doping. In an ESD event, these regions of higher resistivity increase the current gain of the parasitic lateral npn bipolar transistor and thus raise the current It 2 , which initiates the thermal breakdown with its destructive localized heating, thereby improving ESD robustness.

Memory effect in the current-voltage characteristic of a low-band gap conjugated polymer

Abstract: Diodes formed by electrodeposition of the low-band gap polymer poly(4-dicyano methylene-4H-cyclopenta[2,1-b:3,4-b′]dithiophene), onto glass slides coated with indium tin oxide (ITO) and furnished with evaporated aluminum counterelectrodes exhibit a reversible bistability in their current–voltage (I–V) characteristics. Applying +5 V to the ITO electrode induces a “high” conductance state while applying −5 V induces a “low” conductance state. The effect is identical in most respects to recent observations in diodes formed from thin films of chromium-doped SrZrO3 sandwiched between SrRuO3 and gold electrodes. A number of mechanisms are discussed but the evidence points to the controlling influence of an interfacial depletion layer at the ITO–polymer interface. It is also shown that the high capacitances associated with such layers can lead to higher than expected displacement currents being generated during the automated collection of I–V data. The presence of such currents distorts the I–V characteristics i...

Semiconductor integrated circuit device and manufacturing method thereof

Abstract: In the semiconductor integrated circuit device, a first P + type buried layer formed as an anode region and an N + type diffused region formed in a cathode region are spaced from each other in the direction of the depth. This makes it possible to provide a semiconductor integrated circuit device in which a large depletion layer forming region can be provided in an N type region at a PN junction formed by first and second epitaxial layers and when a reverse bias voltage is applied to a diode element and in which a withstand voltage can be maintained by a depletion layer thus formed to prevent breakdown of elements in the device attributable to a breakdown current.

Insulated gate semiconductor device having field shaping regions

Abstract: A semiconductor body (10) has first and second opposed major surfaces (10a and 10b), with a first region (11) of one conductivity type and a plurality of body regions (32) of the opposite conductivity type each forming a pn junction with the first region (11). A plurality of source regions (33) meet the first major surface (10a) and are each associated with a corresponding body region (32) such that a conduction channel accommodating portion (33a) is defined between each source region (33) and the corresponding body region (32). An insulated gate structure (30,31) adjoins each conduction channel area (33a) for controlling formation of a conduction channel in the conduction channel areas to control majority charge carrier flow from the source regions (33) through the first region (11) to a further region (14) adjoining the second major surface (10b). A plurality of field shaping regions (20) are dispersed within the first region (11) and extend from the source regions (32) towards the further region (14) such that, in use, a voltage is applied between the source and further regions (33 and 14) and the device is non-conducting, the field shaping regions (20) provide a path for charge carriers from the source regions at least partially through the first region and cause a depletion region in the first region (11) to extend through the first region (11) towards the further region (14) to increase the reverse breakdown voltage of the device.

Transistor and method of manufacturing the same

Abstract: A technique for reducing an on-resistance of a transistor is provided A power MOSFET of the present invention has a semiconductor material which is disposed under a polysilicon gate and composed of polysilicon into which impurities are doped at low concentration Therefore, a depletion layer is expanded to the inside of the semiconductor material under the polysilicon gate Since the electric field strengths are uniform from the surface of a drain layer to a depth of the bottom surface of the semiconductor material and a high electric field is not generated at one site, the avalanche breakdown voltage of the transistor is increased Therefore, the concentration of impurities in drain layer can be made higher than that in a conventional transistor and thereby the on-resistance of the transistor 1 can be reduced

High voltage semiconductor device having a field plate arrangement

Abstract: A semiconductor body (11) has first and second opposed major surfaces (11a and 11b). First and second main regions (13 and 14) meet the second major surface (11b) and a voltage-sustaining zone is provided between the first and second regions (13 and 14). The voltage-sustaining zone has a semiconductor region (11) of one conductivity type forming a rectifying junction (J) with a region (15) of the device such that, when the rectifying junction is reverse-biased in one mode of operation, a depletion region extends in the semiconductor region of the voltage-sustaining zone. A number of conductive regions (22) are isolated from and extend through the semiconductor region (11) in a direction transverse to the first and second major surfaces (11a and 11b) so as to be spaced apart in a direction between first and second main regions. A voltage regulator (20; 20'; 20a and 20b) is provided for setting the voltage at each conductive regions (22) so as to control the voltage distribution, and thus the electrical field profile, in the voltage- sustaining zone when the rectifying junction is reverse-biased in said one mode of operation.

Dynamics of the second-order nonlinearity in thermally poled silica glass

Abstract: We study the temporal evolution of both the second-order nonlinear coefficient and of the nonlinear thickness in thermally poled silica-glass slides by using a high-resolution all-optical technique. A time delay in the nonlinearity formation is observed, followed by an increase to a maximum, and a final decrease. The thickness is shown to increase at a rate that differs significantly from that reported for the corresponding ionic charge fronts. Our measurements also show strong dependencies on sample thickness and these can be attributed to different electric fields in the depletion region.

Semiconductor device having a plurality of resistive paths

Abstract: A semiconductor device has first and second opposed major surfaces (10 a and 10 b). A semiconductor first region (11) is provided between second (12 or 120) and third (14) regions such that the second region (12 or 120) forms a rectifying junction (13 or 130) with the first region (11) and separates the first region (11) from the first major surface (10 a) while the third region (14) separates the first region (11) from the second major surface (10 b). A plurality of semi-insulating or resistive paths (21) are dispersed within the first region (1′) such that each path extends through the first region from the second to the third region. In use of the device when a reverse biasing voltage is applied across the rectifying junction (13 or 130) an electrical potential distribution is generated along the resistive paths (21) which causes a depletion region in the first region (11) to extend through the first region (11) to the third region (14) to increase the reverse breakdown voltage of the device. The device may be, for example a pn-n diode in which case the second region is a semiconductive region of the opposite conductivity type to the first region or a Schottky diode in which case the second region (120) forms a Schottky contact with the first region.

Image sensor, method of fabricating the same, and exposure apparatus, measuring device, alignment device, and aberration measuring device using the image sensor

Abstract: In the present invention, a charge transfer unit is arranged on a first-plane side of a thinly-formed semiconductor base. Charge accumulating units are arranged on a second-plane side, the opposite side. A depletion prevention layer is arranged closer to the second-plane side than the charge accumulating units. The depletion prevention layer prevents a depletion region around the charge accumulating units from reaching the second plane of the semiconductor base. The depletion prevention layer can suppress surface dark current going into the charge accumulating units. Meanwhile, an energy ray incident from the second-plane side pass through the depletion prevention layer to generate signal charges in the charge accumulating units (depletion regions). The charge accumulating units collect, on a pixel-by-pixel basis, the signal charges which are to be transported to the charge transfer unit under voltage control or the like, and then are read to exterior as image signals.

Method and apparatus for isolating circuits using deep substrate n-well

Abstract: Techniques to isolate noise-sensitive circuits from noise generated by nearby circuits. In one design, a quiet region is formed on a die when surrounded by a deep n-well formed on top of a p-type substrate. The deep n-well is heavily doped n-type and forms a depletion region at the junction with the p-type substrate. The depth and width of the depletion region is dependent on the doping concentration of the deep n-well and the amount of reverse bias voltage applied to the deep n-well. In general, a wider and deeper depletion region may be formed by more heavily doping the deep n-well and applying a higher reverse bias voltage. By properly constructing the deep n-well and applying a high reverse bias voltage, a deep and wide depletion region may be formed to provide a barrier against noise from entering the quiet region.

A comprehensive study of inversion current in MOS tunneling diodes

Abstract: The gate current of MOS tunneling diodes biased at inversion region with different substrate doping is investigated. For p-type substrate (1-5 /spl Omega/-cm) devices, the tunneling diode works in the deep depletion region and the inversion current is dominated by the thermal generation rate of minority electrons via traps at Si/SiO/sub 2/ interface and in the deep depletion region. The activation energy is approximately equal to half of the silicon bandgap independent of gate voltage. For devices on p/sup +/ substrate (0.01-0.05 /spl Omega/-cm), the band-to-traps tunneling and band-to-band tunneling are the dominating current components at inversion bias, and reveal a strong field dependence and a weak temperature dependence. The band-to-traps and band-to-band current components are even more significant in the devices on the p/sup ++/ substrate (0.001-0.0025 /spl Omega/-cm). Finally, the effects of temperature and light illumination on inversion current of MOS tunneling diodes will be also discussed.

Schottky diode and its manufacturing method

Abstract: PROBLEM TO BE SOLVED: To lower ON resistance without lowering a field relaxing effect in the reverse direction and to reduce the loss by reducing an ON voltage in the forward direction. SOLUTION: A plurality of p-type diffusion layers 3 are formed on the surface layer of an n - -type epitaxial layer 2. The p-type diffusion layers 3 is arranged such that a lower region 3b is wider than an upper region 3a and the distance between adjacent p-type diffusion layers 3 is shortened in the lower region 3b. In such a Schottky diode, each p-type diffusion layer 3 is pinched off by a depletion layer extending from the lower region 3b of each p-type diffusion layer 3 and a field is relaxed in the reverse direction. Since the upper region 3a of the p-type diffusion layers 3 is made narrow, a contact part of the n - -type epitaxial layer 2 with a Schottky electrode 5 is widened and contact resistance between the n - -type epitaxial layer 2 and the Schottky electrode 5 can be reduced while increasing a current passage resulting in low ON resistance. COPYRIGHT: (C)2002,JPO

Method for joining and an ultra-high density interconnect

Abstract: Embodiments of the invention are directed to a method comprising depositing a dielectric layer on a circuitized layer having a conductive region. The dielectric layer is preferably a bonding sheet. An aperture is formed in the dielectric layer over the conductive region. A conductive body, disposed on another circuitized substrate, is inserted into the aperture. The conductive body comprises a main region (e.g., a conductive post) and a depletion region (e.g., a thin layer of metal or transient liquid alloy bonding material). The depletion region contacts the conductive region on the circuitized layer, and the circuitized layers are laminated together. Heat and pressure can be applied to the combination in order to form an intermetallic region from the depletion region.

MOS semiconductor device and method of manufacturing the same

Abstract: The object of the present invention is to suppress a short channel effect on a threshold voltage. A channel region 5 , a pair of source-drain regions and an isolating film 2 having a trench isolation structure are selectively formed in a main surface of a semiconductor substrate 1 . An upper surface of the isolating film 2 recedes to be lower than an upper surface of the channel region 5 in a trench portion adjacent to side surfaces of the channel region 5 and to be almost on a level with the upper surface of the channel region 5 in other regions. Consequently, a part of the side surfaces of the channel region 5 as well as the upper surface thereof are covered by a gate electrode 4 with a gate insulating film 3 interposed therebetween. A channel width W of the channel region 5 is set to have a value which is equal to or smaller than a double of a maximum channel depletion layer width Xdm. Moreover, a width of the trench adjacent to the side surfaces of the channel region 5 is set to be equal to or smaller than a double of a thickness of the gate electrode 4.

Technique for suppression of edge current in semiconductor devices

Abstract: A passive mechanism suppresses injection, into any active guard regions interposed between the edge (170) of a photodiode array chip and the outer photodiode pixels or into the outer pixels themselves, of minority carrier (180) current generated in the physically disrupte region at the egde of the semiconductor die created by cleaving, sawing or otherwise separating the chip from the remainder of the wafer on which the die was fabricated A thin metallic layer covers all or part of the edge region, thereby creating a Schottky barrier This barrier generates a depletion region in the adjacet semiconductor material The depletion region (160) inherently creates an energy band distribution which preferentially accelerates minority carriers generated or near the metal-semiconductor interface towards the metal, thereby suppressing collection of these carriers by any active regions of the guard structure or by the photodiode pixels

Reversible electrical switching at the Bi2Sr2CaCu2O8+y surface in the normal metal – Bi2Sr2CaCu2O8+y single crystal heterojunction

Abstract: We have studied the electronic instability of Bi 2 Sr 2 CaCu 2 O 8+ y -based heterojunctions effected by an electric field. The instability has been shown to be dictated by a change in the number of carriers in the surface depleted layer under influence of an electrical field to about 10 5 V/cm.

Heterojunction bipolar transistor

Abstract: The bipolar transistor of the present invention includes a Si collector buried layer, a first base region made of a SiGeC layer having a high C content, a second base region made of a SiGeC layer having a low C content or a SiGe layer, and a Si cap layer 14 including an emitter region. The C content is less than 0.8% in at least the emitter-side boundary portion of the second base region. This suppresses formation of recombination centers due to a high C content in a depletion layer at the emitter-base junction, and improves electric characteristics such as the gain thanks to reduction in recombination current, while low-voltage driving is maintained.

High frequency switch circuit device

Abstract: A high frequency switch circuit device includes an FET to be a switching element on a semiconductor substrate. The FET includes an n-type well, a gate electrode, a source layer and a drain layer. An n-type well line to be connected to an n-type well layer to be a back gate is connected to a voltage supply node via an inductor. The flow of a high frequency signal between the voltage supply node and the n-type well layer is blocked by the inductor, and the flow of a high frequency signal in the vertical direction is blocked by a depletion layer extending between the n-type well and a p-type substrate region. Moreover, the flow of a high frequency signal in the horizontal direction is blocked by a trench separation insulative layer.

Body bias dependence of 1/f noise in NMOS transistors from deep-subthreshold to strong inversion

Abstract: Dependence of 1/f noise on the body-to-source junction bias voltages (V/sub BS/) between -25 and 05 V for 025-/spl mu/m NMOS transistors is reported In subthreshold, 1/f noise is reduced by about one order of magnitude, when the body-to-source junction is forward biased by 05 V (V/sub BS/) compared to that for V/sub BS/=0 V, which is due to increased depletion layer capacitance as well as possibly due to an increased average distance between oxide traps and carriers caused by the forward bias On the contrary, in strong inversion, 1/f noise remains almost constant for the entire V/sub BS/ range

High withstand voltage semiconductor devices

Abstract: A plurality of trenches (12) are formed in a drift region between a p-type body region (2) and an-type buffer region (4). A silicon oxide film (13) is formed on the side and bottom of each of the trenches (12), and an SIPOS film (14) is buried into each of the trenches. The trenches (12) are formed by RIE, and the SIPOS film (14) is deposited by LPCVD and an undesired portion can be removed by dry etching such as RIE. The SIPOS film (14) is connected to a source electrode (7) at the source end of each trench (12), and it is connected to a drain electrode (8) directly or through a resistor at the drain end thereof. When a high voltage is applied, a depletion layer expands in the n-type drift region (6) from an interface between the n-type drift region (6) and the trench (12) on each side of the n-type drift region (6), therefore, the impurity concentration of the n-type drift region (6) can be heightened without lowering the high breakdown voltage, and the resistance of the drift region can be decreased.

Method and apparatus for exciting a microdischarge

Abstract: A discharge device has a diode with a depletion region, a channel extending through a surface of the diode, and a gas within the channel. The gas is excited and a discharge formed by reverse biasing the diode and establishing an electric field in the depletion region of the diode.

Junction properties of nickel phthalocyanine thin sandwich film structures using dissimilar electrodes

Abstract: Multilayer sandwich structures of Au/NiPc/Pb were fabricated in-situ utilising a sequential deposition technique. Electrical measurements were performed on both in-situ and oxygen-doped samples. Under forward bias conditions, at low voltages, Ohmic conduction, and at higher voltages SCLC were identified. However, in the reverse bias, a transition from electrode limited to bulk limited conduction process was evident. Depletion region width as well as the potential barrier height (φb) at the NiPc/Pb interface were calculated from the reverse J-V characteristics yielding values of 183 nm and 1.03 eV, respectively. After exposure to dry air a strong rectifying effect was observed. The latter is suggested to be associated with the change in the work function of NiPc as a result of oxygen adsorption. The potential barrier height for oxygen-doped samples was calculated yielding a value in the range of 0.955-0.96 eV. Hole and trap parameters, for both in-situ and oxygen-doped sample devices were also evaluated. Derived values suggested that trap concentration associated with higher voltage characteristic is significantly higher for the oxygen-doped sample. This type of behaviour is strongly believed to be due to an oxidisation process occurring near the NiPc/Pb interface.

Transport anisotropy in microcrystalline silicon studied by measurement of ambipolar diffusion length

Abstract: We have studied charge transport anisotropy in microcrystalline silicon (μc-Si:H) by comparing diffusion length measured parallel to the substrate by steady stage photocarrier grating and perpendicular to the substrate by surface photovoltage method (SPV). We have developed a SPV evaluation procedure which allowed us to exclude the effect of light scattering at the naturally rough surface of the μc-Si:H. The procedure allows us to deduce not only the diffusion length, but also the depth of the depletion layer at the surface and recombination coefficients at both top and bottom interfaces of the film. With growing μc-Si:H film thickness the size of the crystallites increases, leading to higher roughness and thus also light scattering. At the same time density of grain boundaries decreases, resulting in an increase of the diffusion length and of the surface depletion layer depth. For all samples the diffusion length perpendicular to the substrate was several times higher than the diffusion length parallel to it, clearly confirming previous indication of the transport anisotropy resulting from the measurements of coplanar and sandwich conductivity.

A PMOS tunneling photodetector

Abstract: A metal/oxide/n-Si structure with ultrathin gate oxide is utilized as a photodetector. At inversion gate bias, the dark current and photocurrent are determined by both the minority carrier (hole) generation rate in the deep depletion region and the electrons tunneling from the gate electrode to n-type Si, while only the former component is significant in the NMOS photodetector. The electron tunneling current dominates the photocurrent at sufficiently large negative gate voltage, and the sensitivity of PMOS detectors is, therefore, enhanced by approximately one order of magnitude, as compared to NMOS detectors.