Showing papers on "Digital electronics published in 1982"

A Temporal Logic for Multi-Level Reasoning About Hardware,

Abstract: : The paper describes a logical notation for reasoning about digital circuits. The formalism provides a rigorous and natural basis for device specification as well as for proving properties such as correctness of implementation. Conceptual levels of circuit operation ranging from detailed quantitative timing and signal propagation up to functional behavior are integrated in a unified way. A temporal predicate calculus serves as the formal core of the notation, resulting in a versatile tool that has more descriptive power than any conventional hardware specification language. The logic has been applied to specifying and proving numerous properties of circuits ranging from delay elements up to the AM2901 ALU bit slice. Presentations of a delay model and a multiplication circuit illustrate various features of the notation.

A unified switching theory with applications to VLSI design

Abstract: Classical switching theory is shown to have deficiencies when applied to the analysis and design of MOS VLSI circuits. A new logic design methodology called CSA theory is described here which overcomes many of these deficiencies. It is based on three primitive component types: connectors that perform wired-logic operations, switches representing controlled connectors, and attenuators representing resistive load devices. Four basic types of logic values are recognized: Boolean 0 and 1 values, unknown or indeterminate U values, and the high-impedance state Z. The number of logic values can be increased systematically to improve modeling accuracy using a concept of logical strength, which corresponds to current drive capability in analog circuits. It is shown that both the behavior and layout of most types of MOS logic circuits, including contact, gate, and nonclassical mixed circuits, can be treated in a uniform and rigorous manner using CSA network models with either four or seven logic values. The use of a digital charge-storage element called a well to represent sequential behavior is examined. CSA theory is applied to two VLSI design issues, inverter synthesis and fault simulation.

Large-Scale Integration of Hybrid-Method Digital Subscriber Loops

Abstract: This paper reports on studies concerning the feasibility of large-scale integrated realization of the circuits needed to provide hybrid-mode full-duplex digital transmission at 80 kbits/s or higher rates over standard local telephone loops. Alternative means of achieving the required 60 dB or so of echo cancellation have been studied in detail. The conclusion is that a combination of analog and digital circuit techniques permit practical MOSLSI realization of the complete modem, including filters, echo canceller, timing recovery, and A/D and D/A converters, without need for external circuit elements, trimming, or adjustments. The preferred system configuration has been evaluated by means of analysis, simulation, and laboratory and field measurements. A complete full duplex system, including an experimental NMOS integrated circuit echo canceller, was built and tested. Measurements showed a bit error rate lower than l0^{-8} with line attenuation up to 40 dB, operating at 80 kbits/s. We conclude that a fully integrated MOSLSI ciruit to implement all functions for a hybrid-mode digital local loop is entirely feasible.

The wire-limited logic chip

Abstract: Highly integrated complex logic chips contain large amounts of wiring. Characteristics of a chip that is physically dominated by wires are examined.

RELAX: A New Circuit Simulator for Large Scale MOS Integrated Circuits

Abstract: Algorithms and techniques used in RELAX are described. RELAX is a time domain MOS digital circuit simulator based on a new analysis method called Waveform Relaxation Method [1] which exploits decomposition techniques. Preliminary comparisons between RELAX and the standard circuit simulator SPICE2 have shown that RELAX is a fast and reliable circuit simulator.

High speed GaAs integrated circuits

Abstract: Much interest has been expressed in the use of GaAs MESFET's for high speed digital integrated circuits (IC's). Propagation delays in the 60- to 90-ps/gate range have been demonstrated by several laboratories on SSI and MSI logic circuits. Recently, large scale digital IC's with over 1000 gates have been demonstrated in GaAs. In this review paper, the device, circuit, and processing approaches presently being explored for high speed GaAs digital circuits are presented. The present performance status of high speed circuits and LSI circuits is reviewed.

Signature analysis system for testing digital circuits

Abstract: A signature analyzer for testing digital circuits includes a memory which is initially programmed with a set of signatures characterizing the digital signals on the nodes of a correctly operating circuit. The nodes of a test circuit are then sequentially applied to a signature generator formed by a multi-stage shift register having the outputs of selected stages fed back to a gate to which the digital signal is applied. The signature generated by the shift register is compared to each of the signatures stored in memory until a signature match is found, thus indicating that the digital circuit, at least as far as the test node is concerned, is operating correctly. The signature generated by the shift register consists of twenty-four bits to provide a probability of error which is comparable to the probability of error in comparing a sixteen-bit signature with the signature from a specifically identified node. At the conclusion of a gate period. sixteen bits of the signature are displayed as four hexedecimal digits In order to minimize the probability of error, the analyzer also counts the number of transitions of the digital signal during the gate period and compares the count to transition counts stored in memory for the digital signals on the nodes of a correctly operating circuit. A comparison is then made of the transition count at the test node with each of the transition counts stored in memory. The analyzer thus ensures a transition count match as well as a signature match.

An Analytic Signal Approach for Transmultiplexers: Theory and Design

Abstract: A new non-FFT approach to transmultiplexer implementation is presented, based on the theory of the baseband analytic signal and on its successive allocation in the FDM format by appropriate digital interpolation and filtering. The method allows wide transition bandwidths to the filters, avoids the use of any product modulator, and leads to a channel-by-channel structure. As a design example, the applicatiion to the 12-channel FDM primary group is Considered in detail, using FIR digital filters realized by 16 bit arithmetic standard digital Circuits. The analysis and the computer simulation of the system performance are finally reported, showing the actual feasibility of the method for the transmultiplexer implementation.

A 4-valued ECL encoder and decoder circuit

Abstract: The authors present the prototype of a 4-valued ECL encoder and decoder circuit that has been designed as a test chip for the realization of 4-valued cells to be used in interconnection networks. The hardware implementation of such a network in a SIMD or a MIMD computer architecture leads to a significant reduction of the number of wires. Static and dynamic characteristics are presented together with results on the propagation of 4-valued signals. Noise margins are compared for 2-valued and 4-valued versions.

Relax: A new circuit for large scale MOS integrated circuits

Abstract: Algorithms and techniques used in RELAX are described. RELAX is a time domain MOS digital circuit simulator based on a new analysis method called Waveform Relaxation Method [1] which exploits decomposition techniques. Preliminary comparisons between RELAX and the standard circuit simulator SPICE2 have shown that RELAX is a fast and reliable circuit simulator.

D4 Digital Channel Bank Family: Dataport — Channel units for digital data system 56-kb/s rate

Abstract: The single-channel dataports are a series of D4 channel units that convert the digital signal derived from one T-facility time slot by the D4 common circuits to an appropriate format at speeds of 64, 9.6, 4.8, or 2.4 kb/s for use in the Digital Data System (DDS). They come in two formats, the first being the DDS bipolar format for 64 kb/s and the second, for the remaining three speeds, being an EIA RS-449 format. Their error-correction feature ensures 10−8 error-rate performance for a 10−3 error-rate transmission channel. Advances in large-scale integration (LSI) technology have allowed the packaging of all the digital circuit functions needed into the space of a single channel unit. An on-board power converter unit generates the additional current required by the dataports over that needed by regular analog channel units. The local loop side of each channel unit uses integrated technology to achieve signal equalization and timing recovery. Standard DDS remote maintenance features are provided. The dataport channel units are easily installed and removed; they supply economical digital transmission.

Apparatus for testing digital and analog circuits

Abstract: A high-speed, high-resolution testing circuit for both analog and digital circuit packs is described. The testing circuit, which employs data compression techniques, comprises a shift register (22) having an overall length selectively variable under program control, and an arrangement (18) for combining incoming data signals with feedback signals out of predetermined stages of the shift register. The positions of the feedback taps of the variable length shift register are selectively variable under program control (24,26).

A New Method for Improved Delay Characterization of VLSI Logic

Abstract: A new method is described which allows determination of Ton and Toff delays of logic gates on VLSI chips as function of load by frequency measurements, that means with automatic testsystems and computer aided evaluation

Design and Implementation of a Fully Digital DC Servo System Based on a Single-Chip Microcomputer

Abstract: A single-chip microcomputer is used to design a fully digital dc servo system to replace the conventional analog circuits. This microcomputer performs three main tasks: the firing control of a three-phase full-wave thyristor dual converter; the compensation for the nonlinear and loading effect in the converter; and compensations of position loop and rate loop. With no current feedback and minimum components, this dc servo system provides fast transient response and high reliability.

An automatically designed 32b CMOS VLSI processor

Abstract: A 32b CMOS VLSI processor chip designed automatically, including 17K gates of random logic and 2304b RAM will be described. Silicon gate technology offers an average loaded propagation delay of 1.6ns/gate using 2μm design rules.

A Logic Minimizer for VLSI PLA Design

Abstract: This paper describes LOGMIN, a new, interactive computer aided logic design tool. LOGMIN automates the increasingly complex problems of VLSI PLA design which has made the specification, manipulation, minimization and generation of PLAs difficult to do by hand. LOGMIN allows the specification of both combinational functions and sequential machines. Combinational functions may be described using a variety of operators, intermediate variables or PLA code. A State Machine Description Language (SMDL) was developed for the specification of sequential machines. This paper describes the background and motivation for LOGMIN, the algorithms used and the grammar for SMDL. Several examples are provided.

Hit - An Analog/Digital Bipolar VLSI Technology

Abstract: with I2L devices in the digital part is now widely used due to the high performance of its bipolar analog circ2uits and the high packing density of its I L digital circuits (1)(2). As shown in Fig.l, analog/digital compatible VLSI's that include more than lk-analog devices and 10k-digital gates will be required in the near future. It is estimated that even an 80k-gate VLSI with 1.5 ns gate delay time is theoretically possible using I L devices (3). Thus, the I2LLSI approach is one of the most promising for the coming VLSI age. In this paper, HIT (High-density Isolation Technology) a new concept in analog/digital compatible VLSI technology is proposed. Fig.2 shows a cross section of the proposed structure. It includes two essential features High-density isolation utilizing a grooving technique is used, and the n-layer thickness in the digital section is reduced preferentially so that high-speed I2L operation and high-voltage analog operation are optimized simultaneously. Fine patterning lithography (3 pm emitter size) is also introduced to achieve the smallest possible device area. Fig.3 shows a photomicrograph of a portion of the experimental chip. It can be seen that the I2L-circuit pattern hrs been well fabricated. Fig.4 shows the I L gate-delay time obtained from measurement of a 1-collector-gate I2L ring oscillator. A 1.6 ns minimum delay time and a 31 fJ power-delay product were achieved due to the optimized n-layer thickness in the digital section. Operation parameters for npn transistors and I2L devices fabricated on the same chip are summarized in Table 1. High breakdown voltage (BVCBO=20 V) and high cut-off frequency (fT= 2 GHz) for the npn transistors were obtained, as well as high speed and low-power dissipation for the I2L devices. In Fig.5, the device-cell areas of this device are compared to those made by conventional planar technologies. Remarkable cell-area reduction (less than 1/10 for the npn transistors and less than 1/5 for the I2L gate) have been achieved. Thus, nearly an order of magnitude increase in packing density of LSI's is possible. High-speed LSI performance is demonstrated in Fig.6. Remarkable improvements in both analog and digital processing speeds are achieved. In summary, it has been shown that I2L devices for analog/digital compatible VLSI's with high operating speed, high packing density and low power dissipation can be fabricated using the proposed approach.

Fan out and speed of GaAs SDFL logic

Abstract: Analyses the fan-out capability and speed of a Schottky diode-FET logic (SDFL) gate in the context of an analytical model which links the fan-out to the parameters of the pull-up, pull-down, and switching transistors, and to the supply voltages. The analysis shows that for higher fan-outs increasing the pull-up to pull-down current ratio should increase the speed; and that to some extent the maximum fan-out can be increased by raising the positive supply voltage. It also demonstrates the decrease in the logic swing with the increase of the fan-out. Computer simulation of inverter chains and ring oscillators with different fan-outs is in good agreement both with the analytical model and experimental results. The results lead to an approximate relation between the time delay per gate and fan-out for an SDLF gate.

Integrated circuit including logic array with distributed ground connections

Abstract: Logic arrays which apply outputs to logic circuitry are made to exhibit improved noise characteristics which, in turn, improve performance of the logic circuitry. The improvement is achieved by providing a distributed ground throughout the logic array to provide local closed loop paths for discharge currents generated in the array. In this manner, discharge currents are not allowed to flow in ground or power BUSES and so do not affect the driven logic circuitry.

FAM 21.6: A CMOS Analog Front End for 9600BPS Facsimile Modem

Abstract: TRADITIONALLY, HIGH-SPEED MODEMS are composed of VLSI chip sets with the analog front end chips separated from the digital processors’. While the digital circuits operate with a single 5V power supply, the analog front end circuits always require higher voltage (usually ? 5V). Therefore, different processes often have to be used for fabricating analog and digital chips to optimize the performance of each. In this paper, a 5V only analog front end for high-speed modems using a standard 2pm CMOS process will be described. The analog front end has been developed to be fabricated on the same chip with the Digital Signal Processor (DSP). Because of the high dynamic range requirement of the QAM high speed signal and the 5V power supply limit, a fully differential architecture has been adopted. Upon reception, the signal is converted to differential, and all of the internal operations thereafter are fully differential. With the differential approach, dynamic range theoretically is doubled and Power Supply Rejection Ratio (PSRR) is improved. In switched capacitor implementations, switching noise is also reduced.

Design and evaluation of a bipolar tri-state logic family

Abstract: A three-valued bipolar logic family utilizing the two conventional TTL logic states plus the high impedance state is described. The functions realized permit the use of existing synthesis algorithms. The noise immunity for such circuits is defined and calculated. A comparison of circuit complexity between the three-valued family and binary TTL is made for three- and two-valued functions with approximately the same number of possible inputs.

Structured Logic Design of Integrated Circuits Using the Storage/Logic Array (SLA)

Abstract: The Storage/Logic Array (SLA), a form of structured logic derived from PLA's, will allow development of sophisticated computer aids for VLSI design. The AND and OR planes of PLA's are folded into a single AND/OR plane. The SLA is described and comparisons with programmable logic arrays (PLA's) are made. Segmenting SLA's with arbitrary row and column breaks results in functional duality of SLA columns and allows embedded memory elements. Arbitrary SLA cell placement permits topological optimization of modules and interconnect. SLA program logic symbols map directly to IC layouts. Cell set realizations of SLA's in I/sup 2/L, NMOS, and CMOS are described and compared. I/sup 2/L designs are not very practical, suffering from poor fanout. Static NMOS SLA circuits provide excellent fanout, but result in high power consumption. CMOS SLA circuits use single, identical Schottky diodes for both AND and OR planes, giving dense circuits with good potential for VLSL. Programming techniques and examples are given.

MAIL-a new Josephson logic family

Abstract: A novel family of Josephson logic circuits called magnetically coupled asymmetric interferometer logic (MAIL) has been designed. The basic MAIL device is an asymmetric two-Josephson-junction interferometer. Computer simulations of OR/AND MAIL circuits using 2.5 /spl mu/m Pb/Pb technology device models indicate an unloaded logic-gate delay of approximately 25 ps and a power dissipation of 5 /spl mu/W/gate. Thus, the power-delay product is only 125 Atto J. Different MAIL logic gates have been tested experimentally, and preliminary results are presented.

A digital phase-locked loop for generating frequency discriminating digital words

Abstract: The circuit configuration of the DPLL described in this paper is a modified version of the DPLL recently reported by the authors. Fast and symmetrical tracking has been achieved by the modified DPLL retaining the original properties of wide locking range and low frequency capability as an FM discriminator and frequency multiplier. Also, it is operable in a number of modes defined by their phases (0°, 180°, and 90°) and the frequency discriminating code X is scalable by the phase-lock logic design.

Manufacturing tolerance of capacitor coupled GaAs FET logic circuits

Abstract: Interstage coupling of depletion mode GaAs digital circuits by means of capacitors has been proposed as a simply fabricated technique combining both low power and process tolerance. This is now substantiated by results of ring-oscillators and dividers, operating at up to 1 GHz, on wafers over which the FET pinch-off voltages vary between -0.5 V and -4.0 V.

Digital servo device

Abstract: PURPOSE:To alleviate the load of an arithmetic controller by composing all circuits as a rule in all of digital circuits and performing the calculation and signal processing processed by program partly by the digital circuits. CONSTITUTION:Moving information of an article is detected by a moving information detector 10, and information for driving and controlling a DC motor 1 is formed by an arithmetic controller 10 from the moving information and reference position information. A pulse width modulator 30 pulse-width-modulates on the basis of the driving and controlling information of the motor 1. A motor drive circuit 40 supplies a drive power to the motor 1 in accordance with the pulse signal outputted from the modulator 30. The drive power of the motor 1 is detected as the current value by a current detecting resistor 51, converted by an A/D converter 52 to a digital signal, and supplied through a feedback circuit 50 to an arithmetic controller 20.

Data playback circuit

Abstract: PURPOSE:To adhieve a data playback circuit of FM code easy of circuit integration without need for time adjustment, by forming a storbe signal with a digital circuit. CONSTITUTION:An input FM code (c) is sampled and stored at the 1/4 period from the start of bit through the leading of a signal (g) at a flip-flop 18, and the output is inputted to an exclusive losical sum circuit 19 with the input signal (c). A signal with the polarity corresponding to the data at the latter half period is appeared at the output of the circuit 19. The point of change of a signal is detected at a flip-flop 13 and an exclusive logical sum circit 14, and based on it, a flip-flot 16 obtains signal to reset a shift register 17. From the shift register 17, a data sampling signal (h) is obtained at the the 3/4 period from the start of bit together with a signal (g) through the step operation.

A subnanosecond cycle time chip in Josephson technology

Abstract: THIS PAPER will describe the design and performance of a subnanosecond cycle time logic chip in Josephson technology. A data processing circuit, implemented in 2.5pm Josephson Current Injection Logic (CIL)? has been tested at cycle times as small as 665ps The chip power dissipation was about 350pW. The circuit contained OR gates, AND gates, EX-OR gates and latches - equivalent to 102 logic gates, consisting of 177 devices. The gates were powered by an ac power supply2 which was regulated on chip3. The latch circuits were of a self-resetting type, designed for this application.