Showing papers on "Effective number of bits published in 1998"

Digital-to-analog converter having high resolution and high bandwidth

Abstract: A digital-to-analog converter (DAC) is preferably employed to receive a digital input word and provide an analog output signal to a motor driver in a disk drive servo. The digital input word has a plurality of bit positions for establishing a resolution for the DAC. These bit positions define first and second groups of bits. The DAC comprises circuitry responsive to the first group of bits for producing a pair of analog signals defining a common-mode magnitude and a differential magnitude. The common-mode magnitude is a function of the value of the first set of bits and the differential magnitude is a function of the number of bit positions in the first group of bits. In the DAC: a clock generates a clocking signal; a state machine has an input for receiving the clocking signal, an input for receiving the second groups of bits, and an output for providing a time-varying control signal; switching circuitry has a pair of inputs for receiving the pair of analog signals, an input for receiving the time-varying control signal, and an output for providing a pulse-width and amplitude modulated signal; and averaging circuitry responds to the pulse-width and amplitude modulated signal to producing the analog output signal.

Implementation of multipliers in programmable arrays

Abstract: Implementation of multipliers in an FPGA or similar device containing an array or other aggregation of small processor devices is a significant difficulty, leading to increased cost as a result of the silicon area consumed thereby. There is thus provided a method of multiplying a first number by a second number by use of an array of processing devices, each of said processing devices having a plurality of data inputs, a plurality of data outputs, and an instruction input for control of the function of the processing device, wherein said processing devices and an input for the first number and an input for the second number are interconnected by a freely configurable interconnect, and wherein each processing device calculates a partial product for multiplication of one or more bits of the first number with one or more bits of the second number, and for each processing device: the value received at the instruction input is determined by one or more bits of the first number; data inputs are provided by m bits of the second number, and, if appropriate, a carry input to add a carry from a less significant partial product and/or a summation input to sum all the partial products of the same significance; data outputs are provided as a summation output containing the least significant m bits of the partial product and a carry output containing any more significant bits of the partial product.

A 500 msample/s 6–bit Nyquist rate ADC for disk drive read channel applications

Abstract: The analog-to-digital conversion required in most disk drive read channel applications is designed for good dynamic and noise performance over a wide input frequency range. This paper presents a 500MSam- ple/s 6-Bit ADC and its embedded implementation inside a disk drive read channel, using a 0.35µm CMOS single-poly, triple-metal process. The converter achieves better than 5 effective number of bits (ENOB) for input frequencies up to Nyquist frequency (f in = 1/2f s ) and sampling frequencies f s up to 400MHz. It also achieves better that 5.6 ENOB for input frequencies up to 1/4f s over process, temperature and power supply variations. At maximum speed (f s = 500MHz) the converter still achieves better than 5 ENOB for input frequencies up to f in = 200MHz. Low frequency performance is characterized by DNL < 0.38LSB and INL < 0.2LSB. The converter consumes 225mW from a 3.3V supply when running at 300MHz and occupies 0.8mm2of chip area.

Noise sensitivity of the ADC histogram test

Abstract: In the paper, the authors consider the performance of histogram-based analog to digital converter (ADC) testing under the assumption of input-equivalent wideband noise, which models either noise sources inside the device or unwanted disturbances corrupting the stimulus signal employed for carrying out the test. Theoretical relationships are presented which allow the design of the test parameters needed to meet a given test accuracy. Moreover, it is shown, that the histogram test is effective in providing information on the deterministic behavior of the tested device and that it can be made insensitive to the effects of input-equivalent noise. Finally, the obtained results are employed to determine the test performance in estimating the device effective number of bits, and simulations results are provided which validate the theoretical derivations.

Physical random number generator, method of generating physical random numbers and physical random number storing medium

Abstract: A physical random number generator including a noise source configured to generate a noise signal, an alternating current AC coupling amplifying device which amplifies the noise signal while removing a direct current DC component therefrom by AC coupling to generate an amplified noise signal, an analog/digital A/D conversion device having an accuracy of not less than two bits which A/D converts the amplified noise signal to digital values composed of bit data of not less than two bits, and a processing device which processes the amplified noise signal and which processes digital values converted from a processed amplified noise signal to generate random number data of not less than two bits with an increased differential nonlinearity as compared to digital values unprocessed by the processing device.

Digital broadcasting system and method

Abstract: Apparatus and method of achieving diversity in reception of plural digital broadcast signals. A stream of a complete set of code bits is generated from one or more sources of data bits. A first Critical Subset of code bits is chosen or selected for a first channel (e.g. a specified puncturing pattern is applied to the stream of a complete set of code sets). A second (e.g. alternative) Critical Subset of code bits is chosen or selected for a second channel (e.g. a second or alternative puncturing pattern is chosen for the second channel). Further alternative Critical Subsets may be chosen for any additional channels. All the channels are transmitters, some can incorporate time delay to achieve temporal diversity. Moreover, the order of transmitting the code bits on each channel can be it different (for example, the interleaving depths can be different). At the receiver, the stream of Critical Subsets of code bits for all of the channels are simultaneously received and a reconstruction of a complete set of code bits accomplished and the reconstructed code and may be inserted into a single Viterbi decoder. Various weighting functions and reconstruction algorithms are disclosed.

Automated ADC characterisation using the histogram test stimulated by Gaussian noise

Abstract: A broadband variant of the histogram test where Gaussian noise is used as a stimulus signal is presented. A methodology allowing for an automated and extensive characterization of analog-to-digital converters (ADCs) is given. Tolerance and confidence intervals are determined both for the integral nonlinearity (INL) and differential nonlinearity (DNL) vectors, related to the number of samples acquired. Experimental results of the characterization of a VXI waveform digitizer using this methodology are shown.

Techniques for pixel level analog to digital conversion

Abstract: Two techniques for performing pixel level analog to digital conversion (ADC) are reviewed. The first is an over-sampling technique which uses a one bit first order (Sigma) (Delta) modulator for each 2 X 2 block of pixels to directly convert photocharge to bits. Each modulator is implemented using 17 transistors. The second technique is a Nyquist rate multi-channel-bit-serial (MCBS) ADC. The technique use successive comparisons to convert the pixel voltage to bits. Results obtained from implementations of these ADC techniques are presented. The techniques are compared based on size, charge handling capacity, FPN, noise sensitivity, data throughput, quantization, memory/processing, and power dissipation requirements for both visible an dIR imagers. From the comparison it appears that the (Sigma) (Delta) ADC is better suited to IR imagers, while the MCBS ADC is better suited to imagers in the visible range.

Digital-to-analog converter in which an analog output of low order bits is attenuated, and added to an analog output of high order bits

Abstract: A digital-to-analog converter has a first digital-to-analog converter for M bits, for receiving M high order bits of input data of N bits, and then outputting a predetermined analog output, and a second digital-to-analog converter for (N-M) bits, for receiving (N-M) low order bits of the input data, and then outputting a predetermined analog output. An attenuator attenuates the analog output of the second digital-to-analog converter to 1/2 M . An analog operating circuit adds the analog output of the first digital-to-analog converter and the attenuated analog output of the second digital-to-analog converter, and outputs an analog output as a result of addition of those analog outputs.

A 200-MSPS 6-bit flash ADC in 0.6-/spl mu/m CMOS

Abstract: This paper describes a 6-bit flash analog-to-digital converter (ADC) which performs the sampling function in a partial-response, maximum-likelihood (PRML) disk drive read channel. It operates with sampling frequencies up to 200 MSPS and achieves an effective number of bits (ENOB) of 5.5 bits with F/sub in/=50 MHz and 5.0 bits at F/sub in/=100 MHz. It consumes 380 mW at 5 V and occupies 2.7 mm/sup 2/. Other features include a bit-error rate of <1e-10 and a programmable nonlinear transfer function.

Evaluation system for analog-digital or digital-analog converter

Abstract: There is provided an evaluation system for an A-D converter or a D-A converter capable of evaluating factors of a compounded fault and measuring an effective number of bits with a high accuracy and with a reduced volume of computation, independently of a testing frequency. A sine wave signal is applied to an A-D converter under test. Maximal or minimal values of a cosine wave component and a sine wave component in the converted output are aligned. A square root of a sum of squares of samples is formed to determine an instantaneous amplitude. The amplitude of the sine wave signal is interleaved into the series of instantaneous amplitudes. A difference series for the interleaved instantaneous amplitude series is formed by digital moving differentiator means. Alternatively, a Wavelet transform is applied to the interleaved instantaneous amplitude series, and a maximum amplitude therein is detected by a peak finder, and the detected value is delivered as representing an estimated effective number of bits.

Highly parallel pulsed optoelectronic analog-digital converter

Abstract: We characterize the performance of a highly parallel pulsed optoelectronic analog to digital converter. The system is based on a time-domain to wavelength-domain mapping, such that an input analog signal is parallelized using a wavelength-division-demultiplexed scheme. Each parallel wavelength channel is then digitized using conventional, slow electronic analog-digital converters. We use narrow-band signals up to 18 GHz and histogram testing to characterize the system. From the measurements, we deduce the effective number of bits of the system to be /spl sim/6 and /spl sim/5 bits for 4 and 36 giga-samples-per-second (GSPS) sampling rates, respectively.

Device for the generation of analog signals through digital-analog converters, especially for direct digital synthesis

Abstract: A device for the generation of analog signals by means of analog-digital converters comprises a block for the generation of words encoded on N bits and an analog-digital converter whose input is encoded on M bits, M being smaller than N. The device furthermore comprises a sigma-delta modulator, at the output of the first block, the bus being separated into M most significant bits reserved for the input of the analog-digital converter and N-M least significant bits that enter the sigma-delta modulator, the output of this modulator being an M-bit bus that is added to the M output bits of the word generation block by digital addition means, M being smaller than N.

Pulse density modulation based digital-to-analog conversion

Abstract: An approach for converting an M-bit digital input value into an analog output signal involves separately processing the (M-N) number of most significant bits and the N number of least significant bits of the M-bit digital input value. The N number of least significant bits are converted by a pulse density modulator (102) into a pulse density modulated signal. The pulse density modulated signal is processed by a filter (104) to provide a first analog signal. The (M-N) number of most significant bits are processed by a static digital-to-analog converter (106) to provide a second analog signal. The first and second analog signals are combined (108) to provide the analog output signal.

Apparatus and method for recovering information bits from a 64/256-quadrature amplitude modulation treliss coded modulation decoder

Abstract: An apparatus for recovering information bits from in-phase and quadrature components of a stream of quadrature amplitude modulation (QAM) trellis code modulation (TCM) signals is disclosed. Each signal has an in-phase component and a quadrature component. The in-phase component includes a decoded bit and a plurality of uncoded in-phase bits and the quadrature component includes a decoded quadrature bit and a plurality of uncoded quadrature bits. The apparatus includes a reencode and puncturing circuitry, an inverse mapping circuitry, and a recovery circuitry. The reencode and puncture circuitry is adapted to receive the in-phase and quadrature components of a QAM TCM signal for encoding the decoded in-phase and quadrature bits. The reencode and puncture circuitry punctures the encoded in-phase bit with the uncoded in-phase bits to generate an in-phase component index. In addition, the reencode and puncture circuitry punctures the encoded quadrature bit with the remaining quadrature bits to generate a quadrature component index. The inverse mapping circuitry is coupled to the reencode and puncture circuitry to receive the in-phase component index and the quadrature component index for recovering a first set of in-phase bits and a second set of quadrature bits. The recovery circuitry is coupled to the inverse mapping circuitry to receive the first set of in-phase bits and the second set of quadrature bits. The recovery circuitry is also coupled to receive the decoded in-phase and quadrature bits. The recovery circuitry recovers a set of information bits by assembling the received bits.

Analog-to-digital converter having multiple reference voltage comparators and boundary voltage error correction

Abstract: An A/D converter having multiple conversions is described. The first conversion determines the Most Significant Bits of the output digital code and a second conversion determines the Least Significant Bits of the output digital code. A multiple reference voltage comparator for use in an A/D converter is described. The multiple reference voltage comparator allows one set of voltage comparators to be used in creating coarse and fine thermometer codes that respectively determine the Most Significant Bits and the Least Significant Bits of the digital code. Further, a set of error detection voltage comparators is provided to determine errors in the coarse thermometer code and allow correction during encoding of the Most Significant Bits.

Analog successive approximation (SAR) analog-to-digital converter (ADC)

Abstract: An analog successive approximation (SAR) analog-to-digital converter (ADC) is disclosed that is a compromise between a SAR ADC implementation and a fully parallel thermometer-to-binary ADC. The analog SAR ADC utilizes N comparators for N bits of output and does not require a clock system, control logic, decode logic, or thermometer-to-binary decode circuitry. Conversion speed is determined by the comparator rate, and the comparator outputs may be used directly as the ADC outputs. The analog SAR ADC disclosed is a low complexity, low-precision analog-to-digital converter (ADC) that may be used to digitize phone line status information so that it may be communicated across a isolation barrier as digital information.

System and method of soft decision decoding

Abstract: A system and method of soft decision decoding is disclosed. An average signal magnitude is generated from a plurality of message bits. A scale factor is generated in accordance with the average signal magnitude, and soft decision bits are generated by processing the message bits using the scale factor. The scale factor and soft decision bits are transmitted and received across a communication link. The soft decision bits are rescaled using the scale factor and then rounded to the nearest integer value. The rounded values are then decoded. The soft decision bits are generated using a quantization having at least two bits, and soft decision bits are preferably rescaled using at least five bits.

System and method using mode bits to support multiple coding standards

Abstract: Using mode bits, multiple coding standards are supported by a single digital signal processor. The mode bits specify which coding standard is implemented so that the system will perform the correct data manipulation operations for that coding standard. Mode bits are provided for shift fifteen bits operations and shift-and-round operations.

Robust digital modulation and demodulation scheme for radio communications involving fading

Abstract: A digital modulation and demodulation scheme for radio communications which is capable of reducing errors due to fading while maintaining the characteristic of the M-ary modulation and demodulation scheme that it is robust against interferences. At the transmitting side, transmission data are divided in advance into blocks of LN bits length each and each block is divided into N sets of L bits data sequences. Then, orthogonal codes of M bits length each corresponding to L bits codes given by the L bits data sequences are generated, and N sets of orthogonal codes for each block are multiplexed into a multiplexed signal, such that M bits constituting each orthogonal code are dispersed in time in the multiplexed signal. A digital modulation is then applied to a carrier using the multiplexed signal.

Modulation/demodulation method and apparatus

Abstract: In a modulation/demodulation system for an infrared data communication, a three-bit serial-to-parallel converting circuit captures an input signal in units of three bits in synchronism with an input clock, and outputs a three-bit parallel data to a decoder. This decoder converts the three-bit parallel data into a four-bit parallel data having different patterns corresponding to all different patterns of the three-bit parallel data in a one-to-one relation. In this four-bit parallel data, regardless of how the four-bit parallel data are serially arranged, the total length of the continuing “1” bits is two bits at maximum, and the total length of the continuing “0” bits is six bits at maximum. A four-bit parallel-to-serial converting circuit receives the four-bit parallel data, to serially output a serial data in synchronism with a modulation clock. Thus, the data transfer rate can be elevated in the infrared data communication.

Circuit and method for internal refresh counter

Abstract: A counter (450) for generating a series of binary addresses, each of the addresses including a set of one or more most-significant bits. The counter includes circuitry to generate the addresses, including the set of most-significant bits (402), in a first mode and circuitry to generate the addresses (400), excluding the set of most significant bits, in a second mode. The counter is operable to transition between the first and second modes. The counter also includes circuitry to generate the addresses in the first mode in a non-binary count order in which the set of most-significant address bits is a set of least-significant bits in the count order.

Low-voltage, 10 bit switched-current ADC with 20 MHz input bandwidth

Abstract: Fully-differential first-generation switched-current memory cells with common-mode feedforward were used to implement a 15 bit/stage pipelined A/D converter in a standard digital CMOS process The peak effective number of bits (ENOB) for input frequencies over 1 MHz is 743, and with a 20 MHz input signal sampled at 3 M sample/s, the measured SFDR and SNDR are 451 and 408 dB, respectively

Apparatus and method for an error signal compression technique in a fast adaptive equalizer circuit

Abstract: In a transceiver unit including an adaptive equalizer filter unit, apparatus is provided for reducing or compressing the number of bits representing an error signal. The apparatus replaces a plurality of the most significant logic signal bits with a single bits while transferring the sign logic signal bit and the logic signal bits of lesser significance unchanged. Because of the reduction in the number of logic signal bits, the number of components implementing the multiplier unit in the adaptive filter unit can be reduced (i.e., in each stage of the adaptive filter). The reduction of the apparatus implementing the processing the error signal results in the same equilibrium value of the error signal, however, the time to reach this equilibrium value is increased.

Bit detection method in a radio communications system

Abstract: The present invention relates generally to the detection of bits which are protected by repetition, and which, along with their repetitions, have associated soft values available which give a measurement of the reliability of their received values. In particular, the present invention may be used in speech encoding in the GSM mobile communications system, and more particularly to the detection of those class 2 bits called pulse5 bits which are not protected with channel coding. In enhanced full rate (EFS) transmission in GSM there are 4 bits called pulse5 bits. These pulse5 bits are duplicated twice, giving three bits for each original bit, for a total of twelve pulse5 bits. These bits have associated soft values, a probability measure of their reliability, that are produced by the equaliser. These associated soft values are then used in the present invention to improve detection of these pulse5 bits over the state of the art which detects the pulse5 bits only using a majority decision among the 3 bits generated, without using their associated soft values.

AC performance improvement of folding/interpolation ADC with SiGe HBT

Abstract: This paper describes how to improve the accuracy (the number of effective bits) of a folding/interpolation ADC for a high-frequency input signal. First we identify the AC performance limitation as being the analog timing skew between higher-bits and lower-bits of the folding/interpolation ADC. Next we show in theory and by SPICE simulation that a digital error correction with analog timing skew minimizing circuits reduces the analog timing skew problems. Then we show that using a track and hold circuit before the ADC virtually eliminates the need for digital error correction, but the analog timing skew minimizing circuits still improve the AC performance.

Testing high-resolution digitizers using conventional signal sources

Abstract: This paper presents a method to evaluate the performance of high-resolution digitizers using signal sources that may be of lower specification than the device under test. The method is based on the best fitting of a straight line to a set of measures of the signal to noise ratio, excluding the harmonic distortion, obtained for several amplitudes of the test signal. Theoretical derivations and both computer simulated and experimental data are included. It is shown that the effective number of bits estimated using this method is not affected by the leakage effects that occur when other frequency domain tests are used and the input signal is sampled along a non-integer number of cycles.

Differential decoder for orthogonal amplitude modulation system

Abstract: PROBLEM TO BE SOLVED: To provide a differential decoder simple in circuit configuration and capable of reducing the memory capacity of a lookup table. SOLUTION: This differential decoder 10 is provided with a differential decoder 20 that applies differential decoding two bits in received n-bit data, a rotation device 30 that rotates the other (n-2) bits of data in n-bit received in the 1st quadrant based on the 2-bit of the n-bit data received by the differential decoder 20, and a single quadrant de-mapping circuit 40 that assigns the amplitude of the received signal to a value of data bits based on the data in (n-2) bits rotated by the rotation device 30. Then an output signal in 2-bit is obtained from the differential decoder 20 and data in (n-2) bits of the output signal are obtained from the single quadrant demapping circuit 40. COPYRIGHT: (C)1999,JPO

System and method for minimizing clock cycles lost to overhead data in a video decoder

Abstract: A video processing device capable of minimizing clock cycles lost to overhead information includes an encoder for generating first and second groups of overhead bits. The first group includes a fixed number of overhead bits and the second group includes a variable number of overhead bits. A shift register receives pixel data from a data source, receives the second group of overhead bits from the encoder, and provides output of the pixel data and the second group of overhead bits. A multiplexer receives the pixel data and the second group of overhead bits from the shift register, receives the first group of overhead bits from the encoder, and provides output of the pixel data and the first and second groups of overhead bits which are then combined in an output register.