Showing papers on "Electronic packaging published in 2016"

Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices

Abstract: Dedicated multi-project wafer (MPW) runs for photonic integrated circuits (PICs) from Si foundries mean that researchers and small-to-medium enterprises (SMEs) can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved.

Predicted stresses in ball-grid-array (BGA) and column-grid-array (CGA) interconnections in a mirror-like package design

Abstract: There is an obvious incentive for using bow-free (temperature change insensitive) assemblies in various areas of engineering, including electron device and electronic packaging fields. The induced stresses in a bow-free assembly could be, however, rather high, considerably higher than in an assembly, whose bow is not restricted. The simplest and trivial case of a bow-free assembly is a tri-component body, in which the inner component is sandwiched between two identical outer components (“mirror” structure), is addressed in our analysis, and a simple and physically meaningful analytical stress model is suggested. It is concluded that if acceptable stresses (below yield stress of the solder material) are achievable, a mirror (bow-free, temperature-change-insensitive) design should be preferred, because it results in an operationally stable performance of the system.

Pressureless Bonding by Micro-Sized Silver Particle Paste for High-Temperature Electronic Packaging

Abstract: Lead-free bonding in high-temperature electronic components is desirable for realizing eco-friendly technology. A pressureless process is more appropriate for electronic packaging because it enables a more automated manufacturing process and avoids any potential damage caused by application of pressure. Recently, Ag nanoparticles were used without pressure to join materials for high-temperature electronic applications. In this study, a Ag paste of micro-sized particles was proposed for electroless nickel immersion gold (ENIG) nished Cu pressureless bonding owing to its advantages of both cost effectiveness and easy manufacturing process compared to Ag nanoparticle paste. The micro-sized Ag paste was composed of both chestnut-burr-like (CBL) and spherical particles. The weight ratios of CBL to spherical particles were 10:0, 7:3, and 5:5. The bonding process was carried out at 573 K for 60 min in a nitrogen atmosphere. The experimental results showed that all of the sintered layers had an open porous structure. ENIGnished Cu joint using the Ag paste of the 5:5 weight ratio exhibited the shear strength of 18.6 MPa, which is comparable to that of a conventional Pb-5Sn joint. [doi:10.2320/matertrans.MD201513]

Heat-conducting electronic packaging composite and preparation method thereof

Abstract: The invention provides a heat-conducting electronic packaging composite and a preparation method thereof. The preparation method comprises the following steps: mixing nano-alumina, nano-silica, a silane coupling agent KH-551, a gamma-aminopropyltriethoxysilane and water at first, and stirring; drying after filtering; mixing with N-methyl pyrrolidone, pyridine and triphenyl phosphate for reaction; adding lithium chloride and methyl alcohol for further reaction; filtering, flushing with N-dimethyl formamide and drying; re-adding acetone for ultrasonic dispersion; mixing bisphenol A epoxy resin, Neodymium(III) 2,4-pentanedionate and water, heating, and stirring for dissolution; mixing the two mixtures, and stirring while performing ultrasonic treatment; performing water bathing, adding 3,5-diaminobenzoic acid, N-aminoethylpiperazine and trimethyl hexamethylene diamine, stirring, and then conducting vacuum degassing; finally, pouring the mixture into a die for curing to obtain the heat-conducting electronic packaging composite. The heat-conducting electronic packaging composite has excellent heat stability, and meanwhile, has very good heat conductivity and a good heat dissipation effect.

The Electronic Packaging Handbook

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FOWLP electrical performances

Abstract: Fan Out-Wafer Level Packaging (FO-WLP) has been recognized as the main electronic packaging and integration technology. It is cost effective and has good electrical performance as compared to the Silicon Interposer. Currently, there are many different versions of this FO-WLP technology being developed with the objective to increase the routing density. In order to design integrated circuit or package the electrical chip using the FO-WLP, it is essential to characterize electrical parameters. In this paper, the Redistribution Layers (RDL) first version of the FO-WLP electrical parameters and their test structures are provided.

Diamond/copper composite packaging material high in thermal conductivity and preparation method thereof

Abstract: The invention discloses a diamond/copper composite packaging material high in thermal conductivity and a preparation method thereof. The material is formed by sintering Cu-(1-10 wt.%)Ti alloy powder, titanium powder and diamonds through the spark plasma sintering technology, wherein the content of Cu is 40-60% by weight, the content of Ti is 2-10% by weight and the rest is the diamonds. The composite packaging material is good in interface bonding performance and high in compactness, the heat conductivity of the material reaches 425-522 W/m.K, the thermal expansion coefficient of the material is lowered to (7.1-8.3)*10 K, and the compactness is greater than 97%. The diamond/copper composite packaging material high in thermal conductivity and the preparation method thereof have the advantages that the operability is high and the process is simple and can be used for the field of electronic packaging.

Manufacturing method of laminated aluminum matrix composite for electronic packaging

Abstract: The invention relates to a manufacturing method of a laminated aluminum matrix composite for electronic packaging. The method includes the steps that reinforcement powder and aluminum matrix powder are evenly mixed according to different proportions, obtained composite powder with different reinforcement contents is sequentially packaged to cylindrical steel dies to be subjected to cold press molding, and cold press billets are subjected to hot press molding in the inert gas atmosphere, so that the density of the billets is increased, the hot press billets are degassed in a high-temperature vacuum manner and then subjected to hot isostatic pressing densification, and the completely-dense billets are manufactured. The manufacturing method is simple and low in cost, the quality is stable, and the composite has the characteristics of being high in strength and tenacity and good in welding performance and can be applied to the electronic packaging field.

Aluminum-Scandium: A Material for Semiconductor Packaging

Abstract: A well-known aluminum-scandium (Al-Sc) alloy, already used in lightweight sports equipment, is about to be established for use in electronic packaging. One application for Al-Sc alloy is manufacture of bonding wires. The special feature of the alloy is its ability to harden by precipitation. The new bonding wires with electrical conductivity similar to pure Al wires can be processed on common wire bonders for aluminum wedge/wedge (w/w) bonding. The wires exhibit very fine-grained microstructure. Small Al3Sc particles are the main reason for its high strength and prevent recrystallization and grain growth at higher temperatures (>150°C). After the wire-bonding process, the interface is well closed. Reliability investigations by active power cycling demonstrated considerably improved lifetime compared with pure Al heavy wires. Furthermore, the Al-Sc alloy was sputter-deposited onto silicon wafer to test it as chip metallization in copper (Cu) ball/wedge bonding technology. After deposition, the layers exhibited fine-grained columnar structure and small coherent Al3Sc particles with dimensions of a few nanometers. These particles inhibit softening processes such as Al splashing in fine wire bonding processes and increase the thickness of remnant Al under the copper balls to 85% of the initial thickness.

The study of warpage of a flip chip embedded trace substrate

Abstract: It is a trend of electronic packaging for light weight and thin package due to the increasing demand for 3C electronics and adaptive devices. As the device get smaller and lighter the substrate of the package get thinner and more complex. Therefore, it is an issue of substrate warpage due to factors such as shrinkage rate, uneven stress distribution in the substrate, and layout of copper layer, and these warpage can generate failure modes of the electric contacting between solder bump and solder pad[1–4]. Here, we present the investigation of the warpage of the embedded trace substrate of Flip-chip chip size package (FCCSP-ETS). Factors of layer thickness, difference of thermal expansion coefficient, and Young's module difference, and curing temperature are investigated based on Timoshenko beam theory. In addition, a 3D optical profiler and a shadow moire technique were used to verify the warpage of a sample FCCSP — ETS substrate under various process parameters.

A design-of-experiment (DOE) to optimize a SiP design for connectivity applications

Abstract: System-in-Package (SiP) is becoming more and more important in integrating functionality while reducing final product form factors and cost. This is particularly true for mobile applications where continued effort to achieve ever smaller products is continuously pushing development of new materials, components and assembly technologies. An optimization study of a SiP design based on a functional product is discussed in this presentation to address the following: 1. Design optimization to reduce component spacing with varied assembly challenges 2. Substrate stack-up optimization for z-height reduction with coreless substrate technologies 3. Flip chip (FC) bump pad optimization for ball bumped or copper-pillar bumped CMOS silicon's 4. Cost reduction potential to replace SOP with paste printing using u-stencil for flip chip applications 5. Assessment of different MUF and fluxing underfill (FU) materials To accomplish these objectives, two types of bumped silicon wafers/dice, three different substrates and four different materials were implemented in this DOE. Short-looped wafers of an actual live device were bumped with CuP pillar as well as with SnAg ball bumping technologies. All three substrate designs are coreless, as compared with the original POR conventional design. One substrate was designed with the plan-of-record (POR) component spacing on a 6-layer stack-up that results in ∼ 290 um overall z-height; X-Y-Z size reductions were achieved on the alternative 4-layer design that has reduced component spacing as well as a reduced overall z-height of ∼ 190 um; furthermore, embedded trace substrate (ETS) was used as the top layer for the 4-layer designs to ensure improved routing capabilities. Subtle differentiation between these two 4-layer designs is in the die shadow area on the top ETS layer: while one design uses solder mask defined pads (SMD) the other uses the ETS dielectric materials to define the flip chip bonding pads without solder mask (NSMD). The latter design facilitates the MUF flows for ultralow stand-off flip chip solder joints and make it a likely “universal” pad design for both CuP and SnAg flip chip bump attach. Four different MUF materials along with one FU materials were used for DOE assembly: the first MUF is the POR material currently used in HVM production with nominal filler sizes; 2nd MUF is for low warpage applications (especially for thin, coreless substrate); 3rd MUF has a smaller filler size that is optimized for small stand-off flip chip bumps and the last MUF has a much improved thermal conductivity and is assessed here for its fit-for-use in other high thermal density applications. FU used is an underfill material with build-in flux and is opportunistically included here to assess its fit for use for our future products. Overall DOE plans shall be described, preliminary results as well as the screening test plan will be presented in some detail and implication of these interacting factors in improving a SiP design to achieve small form end product will be discussed.

Thermal and Electrical Characterizations of Ultra-Thin Flexible 3YSZ Ceramic for Electronic Packaging Applications

Abstract: This paper presents thermal and electrical characterizations of an ultra-thin flexible 3YSZ (3 mol% Yttria Stabilized Zirconia) ceramic substrate to explore its potential for electronic packaging applications. The thicknesses of the ultra-thin 3YSZ substrates were 20 μm and 40 μm. The flexible thin ceramic substrate can provide not only better modulus for higher robustness in manufacturing, especially in Z-axis direction of modules, but also low thermal resistance for high density 2D (two dimensional) / 3D (three dimensional) power module packaging applications. To better understand the thermal and electrical properties of the ultra-thin flexible ceramic, different measurements were employed. Thermal conductivity was measured at different temperatures by 3-omega method, the results were verified by thermo-reflectance measurement at room temperature. Relative permittivity was measured from 100 Hz to 10 MHz, with dielectric losses determined by dielectric spectroscopy. The dielectric breakdown of t...

Extreme temperature packaging: challenges and opportunities

Abstract: Consumer electronics account for the majority of electronics manufactured today. Given the temperature limits of humans, consumer electronics are typically rated for operation from -40°C to +85°C. Military applications extend the range to -65°C to +125°C while underhood automotive electronics may see +150°C. With the proliferation of the Internet of Things (IoT), the goal of instrumenting (sensing, computation, transmission) to improve safety and performance in high temperature environments such as geothermal wells, nuclear reactors, combustion chambers, industrial processes, etc. requires sensors, electronics and packaging compatible with these environments. Advances in wide bandgap semiconductors (SiC and GaN) allow the fabrication of high temperature compatible sensors and electronics. Integration and packaging of these devices is required for implementation into actual applications. The basic elements of packaging are die attach, electrical interconnection and the package or housing. Consumer electronics typically use conductive adhesives or low melting point solders for die attach, wire bonds or low melting solder for electrical interconnection and epoxy for the package. These materials melt or decompose in high temperature environments. This paper examines materials and processes for high temperature packaging including liquid transient phase and sintered nanoparticle die attach, high melting point wires for wire bonding and metal and ceramic packages. The limitations of currently available solutions will also be discussed.

Carrier-based fan-out 2.5D/3D package structure

Abstract: The invention belongs to the field of electronic packaging, and particularly relates to a carrier-based fan-out 2.5D/3D package structure, which comprises a TSV adapter plate, flip chips, an underfill adhesive, a molding compound, a BGA solder ball and the like, wherein the flip chips are inversely welded on the front surface of the TSV adapter plate; the molding compound packages all the chips and the TSV adapter plate; and the BGA solder ball is implanted into the back surface of the TSV adapter plate. According to the carrier-based fan-out 2.5D/3D package structure, system-in-package is achieved by combining a fan-out technology and an adapter plate technology; the production cost is reduced; reduction of warping is facilitated; the chip offset is reduced; and the feasibility of the process and the reliability of a package body are improved.

Sealed Packages For Electronic And Energy Storage Devices

Abstract: The present disclosure provides insulated assemblies for electronics packaging, the assemblies in some embodiments including an electrical connection extending through a tube that extends through an insulating vacuum space

High throughput thermo-compression bonding with pre-applied underfill for 3D memory applications

Abstract: As demand for smaller and faster electronic products increases rapidly, 3D packaging with higher electrical performance and density are desirable [1]. Flip chip interconnection technologies using copper pillars have been widely used in many microelectronic applications for high performance systems as well as consumer electronics in recent years [2]. The technology offers improved electrical and thermal performance due to shorter electrical paths between die and substrate. Memory applications remain as a key growth segment for 3D packaging due to the drive for reduced package height and increased numbers of stacked die. Traditionally, capillary underfill is applied after the flip chip interconnections are formed. The underfill resin flows into the gap between the die and substrate by a capillary force [3]. However, with shrinking interconnection gaps and the limitations in underfill flow and also inhomogeneity in the resin system, capillary underfill proves to be difficult as it is a slow process and can result in voids between copper pillars in fine-pitch packages [4]. In order to solve these problems, thermo-compression bonding (TCB) processes using preapplied non-conductive film (NCF) were developed and are commonly used in fine pitch devices [5-7]. Due to the high entry equipment investment capital required, additional breakthroughs for a high throughput TCB process is required to enable widespread industrial adoption. Currently, 3D memory stacking using a TCB process is performed layer by layer involving several temperature ramping steps in order to activate, flow, and cure the NCF before reaching the solder melting temperature and completing the solder reflow. Moreover, since NCF is sensitive to high temperatures, there is a cooling step at the end of the bonding process in every layer to cool down the bond head before picking up the next die. Collective bonding, together with K&S APAMA® flip chip bonder patent pending Contactless Transfer feature, is presented in this paper to demonstrate a high throughput TC-NCF process. Collective Bonding is done by tacking all the layers in a memory stack at a lower temperature. After that, a TCB process with higher temperature ramping is performed only at the last layer. For conventional TC-NCF bonding, sub 100°C temperatures during transfer of the die from picker to bond head has to be used, which results in lower throughput. A contactless transfer process allows higher transfer and alignment temperatures to be used, enabling higher UPH as no additional time is required for cooling down of the bond head. In addition, a higher transfer and alignment temperature was shown to reduce NCF voiding issues by removing the volatiles and moisture in the NCF material prior to die placement. Collective Bonding process factors affecting the bondability of interconnect, such as solder wetting and solder thickness control were studied. NCF underfill performance such as voids, fillet control, and film outgassing were also investigated. Lastly, an empirical UPH model will be presented to illustrate potential throughput improvement.

The Design and Evaluation of an Integrated Wire-Bondless Power Module (IWPM) using Low Temperature Co-fired Ceramic Interposer

Abstract: This article presents the plan and initial feasibility studies for an Integrated Wire Bond-less Power Module. Contemporary power modules are moving toward unprecedented levels of power density. The ball has been set rolling by a drastic reduction in the size of bare die power devices owing to the advent of wide bandgap semiconductors such as silicon carbide (SiC) and gallium nitride. SiC has capabilities of operating at much higher temperatures and faster switching speeds compared with its silicon counterparts, while being a fraction of their size. However, electronic packaging technology has not kept pace with these developments. High-performance packaging technologies do exist in isolation, but there has been limited success in integrating these disparate efforts into a single high-performance package of sufficient reliability. This article lays the foundation for an electronic package designed to completely leverage the benefits of SiC semiconductor technology, with a focus on high reliability and fast...

Spiral-body-enhanced metal-based or polymer-based composite and preparation method

Abstract: The invention provides a spiral-body-enhanced metal-based or polymer-based composite and a preparation method. The composite is formed by distributing an array formed by a plurality of spiral enhancing bodies in a metal matrix and combining the surface-modified spiral enhancing bodies with the metal matrix in a metallurgical manner. The metal matrix is made of frequently-used electronic packaging metal materials such as Al, Cu and Ag. The spiral enhancing bodies are formed by depositing diamond on a spiral-body-shaped substrate through a chemical vapor deposition method to obtain lining supporting diamond spiral bodies, and graphene or carbon nanotubes grow in the direction perpendicular to the surface to obtain a spiral diamond heat conductor structure with a vertical-array graphene wall or a carbon nanotube forest on the surface. The high-heat-conductivity composite is obtained by distributing the spiral enhancing bodies in the metal matrix to form an array and adding enhancing particles to further improve the heat conductivity. The composite can be used as electronic packaging, heat sink materials and the like, and the packaging problems of high-temperature, high-frequency and high-power electronic devices are solved.

Low-thermal-expansion high-strength glass-ceramic material and preparation method thereof

Abstract: The invention belongs to the field of electronic ceramic materials, and relates to a low-thermal-expansion high-strength glass-ceramic material and a preparation method thereof. The problems that an existing ceramic material is poor in thermal expansion coefficient and silicon chip matching degree, too small in flexure strength and the like are solved. The material is suitable for electronic packaging, particularly for manufacturing a packaging substrate of a large-scale integrated circuit. The material is prepared from, by weight, 2-6% of Li2O, 10-20% of Al2O3, 50-70% of SiO2, 1-10% of MgO, 1-10% of CaO, 1-10% of ZnO, 2-8% of B2O3, 1-7% of ZrO2 and 1-8% of Cr2O3. The material has a thermal expansion coefficient of 2.1-4.0*10 /DEG C and flexure strength of 150-210 MPa, good thermal matching can be achieved between the electronic packaging substrate prepared from the material and a silicon chip, and the material has high flexure strength, good dielectric performance and reliable insulativity; meanwhile, the glass-ceramic material is simple in production process, high in stability and low in cost.

Development and characterization of graphene enhanced thermal conductive adhesives

Abstract: In this paper, a graphene enhanced thermal conductive adhesive (G-TCA) was developed for thermal management of power devices. The developed G-TCA has many advantages, including high thermal conductivity, lower density, good dispensing ability, and cost effective. To fabricate G-TCAs, few-layer graphene was utilized as fillers to improve the thermal conductivity of the TCA. The graphene nanosheets were fabricated through a high-speed shear mixing process in a mixed solvent. Compared to many reported liquid exfoliation process, the graphene fabrication process shows many advantages, such as high process efficiency, mass production, low-cost, clean and safe process. G-TCA sample with a hybrid filler ratio of 73% Ag and 3% graphene shows the highest thermal conductivity of 8 W/m K, which is almost four times higher than reference TCAs. A Joule heating setup was built to simulate G-TCA's function in a real electronic component and demonstrate the superior heat dissipation properties of the G-TCAs. Viscosities of the G-TCA samples were regulated in an acceptable range of many dispensing processes to be able to make uniform and fine patterns. Therefore, the developed G-TCA could be widely used for thermal management of power devices and electronic packaging area to decrease their working temperatures and extend the lifetime of devices.

Design, simulation and fabrication of liquid cooled LTCC devices utilizing integrated channels

Abstract: Beside the possibilities low temperature co-fired ceramic (LTCC) offers for electronic packaging it also enables the fabrication of micro fluidic elements like channels and embedded cavities. Hence, LTCC facilitate the realization of complex and integrated micro fluidic systems. However, for many power applications it is necessary to have a short thermal path between the power semiconductor and the heat sink. The poor thermal conductivity of LTCC necessitates an opening in the ceramic, to bond the chip directly to the heat sink. The focus of the presented paper lies on the heat dissipation by liquid cooling. For this purpose two cooling methods utilizing liquid cooling are investigated. In method 1 a power chip is placed on a LTCC substrate with an integrated fluidic channel. A coolant is pumped through the channel in order to cool down the device. Thermal vias are added in the ceramic and the fluidic channel to optimize the heat transfer to the coolant. In method 2 the power chip is placed directly in the channel and coolant is pumped through an opening over the chip in order to realize jet impingement cooling. The designs are simulated using ANSYS CFX to estimate the thermal resistance of the devices and to evaluate the influence coolant flow rate. The designs are fabricated using the DuPont 951 tape system in combination with high purity carbon tape to form the fluidic channels inside the LTCC and silver metallization. The jet impingement cooling design is fabricated in two separate LTCC modules, one containing a flip chip mounted thermal test chip (TTC) and one containing the fluidic elements. The two modules are bonded using an aluminum filled epoxy. The TTC is used to evaluate the thermal resistances, which are 3.1 K/W and 1.1 K/W for method 1 and method 2, respectively. Advantages of the presented cooling methods are the low thermal resistance and the good embedding capability in the co-fire LTCC process.

Digitally driven microfabrication of 3D multilayer embedded electronic systems

Abstract: The integration of multiple digitally driven processes is seen as the solution to many of the current limitations arising from standalone Additive Manufacturing (AM) techniques A technique has been developed to digitally fabricate fully functioning electronics using a unique combination of AM technologies This has been achieved by interleaving bottom-up Stereolithography (SL) with Direct Writing (DW) of conductor materials alongside mid-process development (optimising the substrate surface quality), dispensing of interconnects, component placement and thermal curing stages The resulting process enables the low-temperature production of bespoke three-dimensional, fully packaged and assembled multi-layer embedded electronic circuitry Two different Digital Light Processing (DLP) Stereolithography systems were developed applying different projection orientations to fabricate electronic substrates by selective photopolymerisation The bottom up projection orientation produced higher quality more planar surfaces and demonstrated both a theoretical and practical feature resolution of 110 μm A top down projection method was also developed however a uniform exposure of UV light and planar substrate surface of high quality could not be achieved The most advantageous combination of three post processing techniques to optimise the substrate surface quality for subsequent conductor deposition was determined and defined as a mid-processing procedure These techniques included ultrasonic agitation in solvent, thermal baking and additional ultraviolet exposure SEM and surface analysis showed that a sequence including ultrasonic agitation in D-Limonene with additional UV exposure was optimal DW of a silver conductive epoxy was used to print conductors on the photopolymer surface using a Musashi dispensing system that applies a pneumatic pressure to a loaded syringe mounted on a 3-axis print head and is controlled through CAD generated machine code The dispensing behaviour of two isotropic conductive adhesives was characterised through three different nozzle sizes for the production of conductor traces as small as 170 μm wide and 40 μm high Additionally, the high resolution dispensing of a viscous isotropic conductive adhesive (ICA) also led to a novel deposition approach for producing three dimensional, z-axis connections in the form of high freestanding pillars with an aspect ratio of 368 (height of 2mm and diameter of 550μm) Three conductive adhesive curing regimes were applied to printed samples to determine the effect of curing temperature and time on the resulting material resistivity A temperature of 80 °C for 3 hours resulted in the lowest resistivity while displaying no substrate degradation ii Compatibility with surface mount technology enabled components including resistors, capacitors and chip packages to be placed directly onto the silver adhesive contact pads before low-temperature thermal curing and embedding within additional layers of photopolymer Packaging of components as small as 0603 surface mount devices (SMDs) was demonstrated via this process After embedding of the circuitry in a thick layer of photopolymer using the bottom up Stereolithography apparatus, analysis of the adhesive strength at the boundary between the base substrate and embedding layer was conducted showing that loads up to 1500 N could be applied perpendicular to the embedding plane A high degree of planarization was also found during evaluation of the embedding stage that resulted in an excellent surface finish on which to deposit subsequent layers This complete procedure could be repeated numerous times to fabricate multilayer electronic devices This hybrid process was also adapted to conduct flip-chip packaging of bare die with 195 μm wide bond pads The SL/DW process combination was used to create conductive trenches in the substrate surface that were filled with isotropic conductive adhesive (ICA) to create conductive pathways Additional experimentation with the dispensing parameters led to consistent 150 μm ICA bumps at a 457 μm pitch A flip-chip bonding force of 008 N resulted in a contact resistance of 23 Ω at a standoff height of ~80 μm Flip-chips with greater standoff heights of 160 μm were also successfully underfilled with liquid photopolymer using the SL embedding technique, while the same process on chips with 80 μm standoff height was unsuccessful Finally the approaches were combined to fabricate single, double and triple layer circuit demonstrators; pyramid shaped electronic packages with internal multilayer electronics; fully packaged and underfilled flip-chip bare die and; a microfluidic device facilitating UV catalysis This new paradigm in manufacturing supports rapid iterative product development and mass customisation of electronics for a specific application and, allows the generation of more dimensionally complex products with increased functionality

Digital Manufacturing and Performance Testing for Military Grade Application Specific Electronic Packaging (ASEP)

Abstract: I. Abstract This paper will discuss the development of additive manufacturing as a process integration methodology for printed electronics and 3D printed structures. This integration enables the ability to move from printed circuit boards (PCBs) to printed circuit structures (PCS). Historically packaging has been identified as a hierarchical (or levels) approach to interconnect electronic products or systems. Level one packaging addresses the interconnection between bare die and the module while level four moves up in the packaging chain to connections between subassemblies. With the advent of digital manufacturing and emergence of more robust materials, the enabling technology provides a manufacturing tool for building electronic packages with integrated passives (some printed) and actives. This further enables the capability to adjust the form factor to the mission or product requirements - also known as personalization. This ability to become form factor agnostic has produced the ability for printing o...

High-thermal-conductivity diamond-metal composite material and preparation method thereof

Abstract: The invention relates to a diamond-metal composite material. Specifically, the composite material comprises metal matrices and diamond composites. The diamond composites comprise diamond particles and surface coatings compounded on the surfaces of the diamond particles. The invention further discloses a preparation method and application of the composite material. The preparation method is simple, effective, feasible, and low in cost, and the obtained composite material is excellent in performance and has great market prospects in the fields of electronic packaging and heat sink.

The effects of graphene-based films as heat spreaders for thermal management in electronic packaging

Abstract: Graphene-based films (GBF) were fabricated using a chemical conversion process including graphene oxide (GO) preparation by use of Hummer's method, graphene oxide reduction using L-ascorbic acid (LAA), and finally film formation by vacuum filtration. GBF is considered as a candidate material for thermal management, i.e. for removing heat from hotspots in power electronic packaging, due to its high thermal conductivity. In this work, the GBF heat spreading performance in 3D TSV packaging was analysed using finite element methods (FEM) implemented in the COMSOL software. Both size effects and the influence of the thermal conductivity of the GBF heat spreader on the thermal performance of the 3D TSV package were evaluated. Furthermore, the size effects of the thermal conductive adhesive (TCA) underfill between the chip and the printed circuit board (PCB) were analysed. The results obtained are critical for proper design of graphene-based lateral heat spreaders in high power electronic packaging.