Showing papers on "Ground bounce published in 2012"

An Experimentally Verified Active Gate Control Method for the Series Connection of IGBT/Diodes

Abstract: The series connection of insulated gate bipolar transistor (IGBT)/diode devices allows the operation at voltage levels higher than the rated voltage of one IGBT/diode. However, due to individual parameter differences of the series-connected IGBT/diodes, it is difficult to ensure a proper voltage balance between them, and transient or steady-state voltage unbalances could cause the failure of these devices. This paper presents an active gate driver developed by the authors that is suitable for the series connection of IGBTs. The proposed active gate driver achieves the transient and steady-state voltage balance between the series-connected IGBT/diode devices. The effectiveness of the gate driver and the active gate control method has been experimentally validated, and promising results have been obtained.

A novel gate assist circuit for quick and stable driving of SiC-JFETs in a 3-phase inverter

Abstract: A novel gate drive circuit for an SiC-JFET in a bridge circuit that ensures a quick and stable switching has been proposed and demonstrated. The gate voltage of an off-state transistor tends to rise up due to a steep drain-source voltage change caused by turning-on of the transistor in the other side of the bridge circuit. Even though the gate terminal is kept in the off-state by a voltage source, the abovementioned steep voltage change induces a non-off-state voltage across the parasitic inductance in the gate wiring. As a result, the capability of an SiC transistor for high switching speed in a bridge circuit is limited. The novel gate assist circuit using a PNP transistor with additional capacitors can overcome this limit. It was verified experimentally that the new gate assist circuit improves the turn-on delay time by approximately six fold and the turn-off time by 72%.

Power transistor gate driver

Abstract: The present invention relates to a gate driver for a power transistor comprising a first charging path operatively connected between a first voltage supply and a gate terminal of the power transistor for charging the gate terminal to a first gate voltage. A second charging path is connectable between the gate terminal of the power transistor and a second supply voltage to charge the gate terminal from the first gate voltage to a second gate voltage larger or higher than the first gate voltage. A voltage of the second voltage supply is higher than a voltage of the first voltage supply.

High-speed resonant gate driver with controlled peak gate voltage for silicon carbide MOSFETs

Abstract: Parasitic inductance in the gate path of a Silicon Carbide MOSFET places an upper limit upon the switching speeds achievable from these devices, resulting in unnecessarily high switching losses due to the introduction of damping resistance into the gate path. A method to reduce switching losses is proposed, using a resonant gate driver to absorb parasitic inductance in the gate path, enabling the gate resistor to be removed. The gate voltage is maintained at the desired level using a feedback loop. Experimental results for a 1200 V Silicon Carbide MOSFET gate driver are presented, demonstrating switching loss of 230 µJ at 800 V, 10 A. This represents a 20% reduction in switching losses in comparison to conventional gate drive methods.

Method and circuit for compensating pixel drift in active matrix displays

Abstract: An apparatus includes a circuit branch electrically connected to a voltage rail and including a light emitting device connected in series with a drain of a dual gate transistor, a switching transistor configured to apply a data voltage to a first gate of the dual gate transistor in response to a scan signal, a capacitor connected between the first gate of the dual gate transistor and the drain of the dual gate transistor, and a conductor for supplying a control voltage to a second gate of the dual gate transistor. A method of operating the circuit is also described.

Drive circuit for insulated-gate-type switching element

Abstract: Provided is a drive circuit used for driving an insulated-gate-type switching element, and capable of reducing current consumption. This drive circuit is provided with: a constant current source (3) for generating a constant current; and a switching circuit (5) for connecting the gate of the insulated-gate-type switching element (1) to the power-source-electric-potential side via the constant current source (3) when turning on, and connecting the gate of the insulated-gate-type switching element (1) to the reference-electric-potential side via a discharge circuit (4) when turning off. In addition, the drive circuit is provided with: a gate voltage detection circuit (7) for detecting the gate voltage of the insulated-gate-type switching element (1); and a current mode selection circuit (6) for switching the constant current source (3) from a normal current mode to a low-consumption current mode, when it is detected that the insulated-gate-type switching element (1) is turned on, on the basis of the gate voltage detected by the gate voltage detection circuit (7).

Drive circuit for voltage-control type of semiconductor switching device

Abstract: A charging current is supplied to the gate (control terminal) of a driven switching device during an on-state command interval, for raising the gate voltage to an on-state value. Otherwise, discharging of the gate capacitance is enabled, for decreasing the gate voltage to an off-state value. A second switching device is connected between the gate and a circuit point held at the off-state voltage value, and is maintained in an on state while the gate discharging is enabled. At a first time point, the gate voltage rises above a threshold value. At a second time point, a voltage detection circuit detects that that the gate voltage has risen above the threshold value, causing the second switching device to be set in the off state. It is ensured that the delay between the first and second time points is shorter than a minimum duration of an on-state command interval.

Enhanced power gating schemes for low leakage low ground bounce noise in deep submicron circuits

Abstract: Design of complex arithmetic logic circuits considering ground bounce noise, noise immunity, leakage current, active power and area is an important and challenging task in deep submicron circuits. In this paper, a comparative analysis of high performance stacking power gating schemes is done which minimizes the leakage power and provides a way to control the ground bounce noise. The innovative power gating schemes such as stacking power gating, diode based stacking power gating are analyzed which minimizes the peak of ground bounce noise in transition mode for deep submicron circuits. Further to evaluate the efficiency, the simulation has been done using such high performance power gating schemes. Leakage current comparison of NAND gate without power gating and with power gating scheme is done. Finally it is observed that the leakage current in standby mode is reduced by 87.14% over the conventional power gating. It is also found that in stacking power gating, the ground bounce noise has been reduced by 76.28% over the conventional power gating scheme. We have performed simulations using Cadence-Spectre in a 90nm standard CMOS technology at room temperature with supply voltage of 1V. Finally, a detailed comparative analysis has been carried out to measure the design efficiency of high performance power gating schemes. This analysis provides an effective roadmap for high performance digital circuit designers who are interested to work with low power application in deep submicron circuits.

Esd-robust i/o driver circuits

Abstract: An ESD-robust I/O driver circuit is disclosed. Embodiments include providing a first NMOS transistor having a first source, a first drain, and a first gate; coupling the first source is coupled to a ground rail, and the first drain to an I/O pad; providing a gate driver control circuit including a second NMOS transistor having a second source, a second drain, and a second gate; and coupling the second drain to the first gate, the second source to the ground rail, wherein the gate driver control circuit provides a ground potential to the first gate during an ESD event occurring from the I/O pad to the ground rail.

Power-Gating Noise Minimization by Three-Step Wake-Up Partitioning

Abstract: Power gating is able to counter subthreshold leakage in low-power nanometer technology circuits without sacrificing performance. But mode transitions in power-gated circuits are accompanied by large inrush/discharge currents causing inductive bounce noise on the power supply and ground rails. This issue has been addressed by gradually turning on the sleep transistor; but this introduces a fixed lower bound on the delay overhead irrespective of the duration of the sleep period, and takes no account of the effects of changes in the circuit internal nodes during wake-up on the ground bounce noise. We observed the behavior of internal nodes during the sleep-to-active mode transition and identified three distinct stages. This motivates a three-step turn-on scheme and an associated compact power-gating structure that limits the current flowing through the sleep transistor only while the gated block is metastable, but quickly boosts the power supply rail when there are no short-circuit current paths in the logic. This strongly suppresses power gating noise, and also reduces wake-up time. Simulation results of 16-bit arithmetic logic units in 65-nm CMOS technology show that the proposed technique offers the advantage of a wake-up time that scales with the discharged value (during sleep) of the virtual power rail.

Storing Data in a Non-volatile Latch

Abstract: Storing data in a non-volatile latch may include applying a bias voltage to a memristor pair in electrical communication with at least one logic gate and applying a gate voltage to a transmission gate to allow an input voltage to be applied to the at least one logic gate where the input voltage is greater than the bias voltage and the input voltage determines a resistance state of the memristor pair.

Liquid crystal display device for improving the characteristics of gate drive voltage

Abstract: An LCD device can include a liquid crystal display panel having a plurality of gate lines; a controller configured to generate at least four clock signals with different phases; a first gate driver configured to apply a high gate voltage to odd-numbered gate lines in response to at least two of the clock signals; a second gate driver configured to apply the high gate voltage to even-numbered gate lines in response to other clock signals; primary discharge circuits each configured to apply a low gate voltage to the respective odd-numbered gate line in response to a carry signal opposite to a voltage level on one of posterior odd-and-even-numbered gate lines; and secondary discharge circuits each configured to apply the low gate voltage to the respective even-numbered gate line in response to the carry signal opposite to the voltage level on the other one of the posterior odd-and-even-numbered gate lines.

A fast wake-up power gating technique with inducing a balanced rush current

Abstract: Power gating technique is important for saving the leakage power, especially for the very deep-submicron system-on-a-chip designs. Although the multi-threshold voltage CMOS (MTCMOS) technology can enable us to cut down the leaky path easily, the induced power/ground bounce is getting worse and can not wake up from power down mode quickly. In this paper, we propose a new concept of power gating technique by balancing the variations of rush current to accelerate the wake-up procedure for a given power/ground bounce specification. Performance evaluations of a 40-bit ALU circuit using the TSMC 0.18µm CMOS technology show that our proposed power gating technique can achieve a 10.23% reduction in wake-up time while keeping the power bounce specification, as compared with the conventional power gating technique.

Doppler features from wind turbine scattering in the presence of ground

Abstract: The time-varying Doppler signatures of a wind turbine in the presence of ground are simulated and interpreted. Both a point-scatterer model and high-frequency ray tracing are used to simulate the ground effect. The Doppler spectrogram shows two additional blade flashes due to the single and double ground bounce returns. The effects of stationary as well as moving ground are studied.

Semiconductor device and method of controlling analog switch

Abstract: A semiconductor device has an analog switch, in which a P channel transistor and an N channel transistor are connected in parallel between an input terminal and an output terminal; a variable voltage circuit, which variably generates, according to an input voltage applied to the input terminal, potentials of a first gate voltage and first back gate voltage of the P channel transistor and of a second gate voltage and second back gate voltage of the N channel transistor; and a control circuit, which supplies to the variable voltage circuit a control signal controlling the analog switch to be conducting or non-conducting. In response to the control signal causing the analog switch to be conducting, the variable voltage circuit outputs the variable-generated first gate voltage and second gate voltage to the respective gates of the P channel transistor and N channel transistor.

Gate driving circuit for display

Abstract: A gate driving circuit for a display is disclosed. The gate driving circuit utilizes at least one transistor connected in series between an input end of a reference voltage signal and a transistor connected to a node providing a high voltage level for making the at least one transistor share the voltage difference between the source electrode and the drain electrode of the transistor connected to the node. In such a manner, the gate driving circuit can reduce the occurrence of current leakage in the transistor, thereby improving the stability of driving voltage of the gate driving circuit and the reliability of the gate driving circuit.

Scalable gate logic non-volatile memory cells and arrays

Abstract: Scalable Gate Logic Non-Volatile Memory (SGLNVM) devices fabricated with the conventional CMOS process is disclosed. Floating gates of SGLNVM with the minimal length and width of the logic gate devices form floating gate Metal-Oxide-Semiconductor Field Effect Transistor. The floating gates with the minimal gate length extend over silicon active areas to capacitively couple control gates embedded in silicon substrate (well) through an insulation dielectric. The embedded control gate is formed by a shallow semiconductor type opposite to the type of the silicon substrate or well. Plurality of SGLNVM devices are configured into a NOR-type flash array where a pair of SGLNVM devices share a common source electrode connected to a common ground line with two drain electrodes connected to two separate bitlines. The pairs of the NOR-type SGLNVM cells are physically separated and electrically isolated by dummy floating gates to minimize cell sizes.

Diode Based Trimode Multi-Threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders

Abstract: In this paper a high performance diode based trimode Multi-Threshold CMOS (MTCMOS) technique is introduced which minimizes standby leakage current and provides a better way to control the ground bounce noise during sleep to active mode transition using one additional mode i.e. hold mode. Analysis of trimode MTCMOS technique using low power 16-bit full adder has been done for reduction of standby leakage current and ground bounce noise. Further, to evaluate the effectiveness of diode based trimode Multi-Threshold CMOS technique, simulation has been done on low power 16-bit full adder circuit with BPTM 90nm technology at room temperature with supply voltage of 1 V. Diode based trimode Multi-Threshold CMOS technique reduces ground bounce noise by 89.36% and standby leakage current by 19.24% as compared to the standard trimode MTCMOS technique.

A method of programming a split gate non-volatile floating gate memory cell having a separate erase gate

Abstract: During the programming of a non-volatile memory cell, a voltage pulse is applied to an erase gate of the cell a delay time after voltage pulses are applied to the other elements of the cell. The erase gate voltage pulse ends at substantialy the same time as the other voltage pulses end.

Switching circuit, charge sense amplifier including switching circuit, and photon counting device including switching circuit

Abstract: A switching circuit, a charge sense amplifier, and a photon counting device are provided. The switching circuit configured to close and open a connection between a first terminal and a second terminal of a predetermined circuit element, includes: a first transistor comprising a source connected to the first terminal, a drain connected to the second terminal, and a gate; a second transistor comprising a drain, a source, and a gate connected to the drain of the second transistor; a current source configured to supply a current flowing through the drain and the source of the second transistor, to generate a gate voltage of the gate of the second transistor; and a multiplexer configured to receive the gate voltage, a reference voltage, and a control signal, and selectively apply the gate voltage or the reference voltage to the gate of the first transistor based on the control signal.

Four BIT CMOS full adder in submicron technology with low leakage and Ground bounce noise reduction

Abstract: For the design and analysis of complex arithmetic circuits, Ground bounce noise is given an equal importance in the list of low power performance measuring parameters like leakage current, active power, delay and area. In this paper leakage power and the ground bounce noise is considerably reduced by the use of sleep transistor in full adder design. Size of the sleep transistor is determined by transistor resizing approach. 4 bit adder is implemented using 1 bit adder as reference. The simulation shows that, the 1 bit and 4 bit adders are efficient in terms of standby leakage power, active power and ground bounce noise. Simulations have been performed using T-Spice 90nm and 65nm CMOS technology with supply voltage of 5v and 3.3v at room temperature.

Delay line with cell by cell power down capability

Abstract: A delay line with cell by cell power down capability and methods of use are provided. The delay cell includes a first gate transistor coupled to a voltage supply, a second gate transistor coupled to ground, and a reset signal provided to at least one of the first gate transistor and the second gate transistor. The reset signal turns the delay cell on and off.

Detector circuit with low threshold voltage and high voltage input

Abstract: An integrated circuit includes a high voltage transistor having a first terminal coupled to sense a high voltage terminal and a control terminal coupled to a regulated voltage, which is regulated with respect to a ground terminal and is substantially less than a high voltage that the high voltage terminal is adapted to withstand. A logic gate is also included and is coupled to be powered from the regulated voltage. The logic gate has an input threshold that is less than the regulated voltage. An input terminal of the logic gate is coupled to a second terminal of the high voltage transistor. An output of the logic gate is coupled to indicate that a voltage sensed between the high voltage terminal and the ground terminal is less than the input threshold voltage of the logic gate.

Design method for eliminating Ground noise

Abstract: The invention provides a design method for eliminating a Ground noise The method comprises the steps of: 1) directly connecting a negative pin of a decoupling capacitor with a ground pin of a power supply conversion chip when placing a PCB (Printed Circuit Board) apparatus, thereby, eliminating oversized noise caused by inappropriate placement of the decoupling capacitor, and effectively reducing the parasitic inductance and resistance values generated by a long trace path as well as reducing unstability of system voltage caused by ground bounce; 2) adding GNDVIA near the horizontal of the decoupling capacitor C2677/C2678 to reduce the horizontal impedance, effectively reducing the voltage noise within 1mV after adding the GNDVIA, and ensuring the stability of a power supply; and 3) directly connecting the ground pin of the decoupling capacitor directly with a plurality of ground pins of a power supply converter to cut off a coupling path, thereby effectively reducing the current circuit impedance, reducing the ground noise and increasing the stability of voltage

Low Leakage Low Ground Bounce Noise Power Gating Techniques for FPGAs

Abstract: Design complexity is increasing day by day in modern digital systems. Due to reconfigurable architecture, low non recurring engineering (NRE) and ease of design field programmable gate arrays (FPGA) become a better solution for managing increasing design complexity. Due to scaling trends FPGA uses more transistors which increase the leakage current. FPGAs are well suited for wireless applications since they provide high performance computation together with the capability to adapt to changing communication protocols. So if we are able to reduce the leakage power of an FPGA device, then it can be suitable for use in mobile as well as other low power and battery operated applications. So, this paper provides a detailed analysis of benchmark circuit 74182 a high speed carry look ahead adder by using low leakage low ground bounce noise power gating techniques. Techniques stacking power gating, Diode based stacking power gating, and Diode based staggered phase damping technique reduces peak of ground bounce noise and standby leakage current effectively. Diode based staggered phase damping technique is identified as most effective technique with 99% reduction in ground bounce noise and 75% reduction in leakage current. To evaluate the effectiveness of the power gating techniques, the simulation has been performed using BPTM 45nm technology at room temperature with supply voltage of 0.7V. To do the performance analysis we have implemented lookup table ( LUT) of benchmark circuit (74182) in Spartan-3ADSP, 90nm FPGA, Virtex-5, 65nm FPGA, Virtex-6 LP, 40nm FPGA and Kintex-7 FPGA. On comparison with conventional mode, diode based staggered phase damping technique is considered as best case power gating technique for leakage current while diode based stacking power gating technique is classified as best case power gating technique for ground bounce noise and average power with 99% reduction in ground bounce noise and 99.6% reduction in average power. All these results have been done using XILINX ISE 14.1 tool.

Doppler features from wind turbine scattering in the presence of ground

Abstract: The time-varying Doppler signatures of a wind turbine in the presence of ground are simulated and interpreted. Both a point-scatterer model and high-frequency ray tracing are used to simulate the ground effect. The Doppler spectrogram shows two additional blade flashes due to the single and double ground bounce returns. The effects of stationary as well as moving ground are studied.

Semiconductor device with buried gates

Abstract: A method for manufacturing a semiconductor device comprises forming a buried gate after forming an active region to have a line type. The buried gate comprises an operation gate and a non-operation gate. A height of a gate electrode layer (conductive material) of the non-operation gate is formed to be lower than that of a gate electrode layer of the operation gate, thereby increasing a threshold voltage and preventing an overlap of the ion-implanted active region with the non-operation gate. As a result, a Gate Induced Drain Leakage (GIDL) is prevented to improve a refresh characteristic of the semiconductor device.

Phenomenology of ground scattering in tropical forests through polarimetric SAR tomography

Abstract: This paper aims at characterizing the scattering mechanisms occurring at the ground level in a tropical forest illuminated by a P-Band SAR. The analyzed data set is the one collected by ONERA over Paracou, French Guyana, in the frame of the ESA campaign TropiSAR. The favorable baseline distribution of this data set results in the possibility to remove most contributions from the vegetation layer by tomographic techniques, thus allowing a direct investigation of ground scattering. Two major conclusions are drawn: i) double bounce scattering from trunk-ground interactions is observed to be the dominant scattering mechanism at the ground level on flat terrains, whereas it rapidly tend to vanish as the topographic slope increases; ii) the characteristic parameter that rules trunk-ground scattering is not the tree height, but rather the available free path facing the tree, as a result of the presence of nearby trees or understory preventing double bounce scattering from taking place whenever the ground bounce occurs too far away from the considered tree.

Power switch driver, IC (integrated circuit) chip and DC-DC converter

Abstract: The utility model discloses a power switch driver, an IC (integrated circuit) chip and a DC-DC converter, which are used for reducing ground bounce of a switching power supply, keeping a low switching-on speed of a power switch and reducing the impedance from a grid electrode of the power switch to the power supply or the ground when the power switch is switched off, so that the off power switch cannot be instantly conducted by means of coupling of a parasitic capacitor. The power switch driver comprises an NMOS (N-channel metal oxide semiconductor) field effect transistor, a PMOS (P-channel metal oxide semiconductor) field effect transistor, a first resistor and a second resistor, wherein the NMOS field effect transistor is used for controlling a P-type power switch, the PMOS field effect transistor is used for controlling an N-type power switch, the first resistor is connected with a source electrode of the NMOS, and the second resistor is connected with a source electrode of the PMOS.

Model of IGBT Gate Driving Circuit and Its Application

Abstract: Aiming at the losses calculation and power source designing of gate driving circuit for IGBT device,the mechanism of the device's gate controlling transient is analyzed,and the voltage and current equations which can describe the gate operation principle,are expressed based on the equivalent circuit of the device's switching process. Finally,the formula of gate power losses calculation is given.The simulation and experimental results show that the model can describe IGBT device's gate characteristic precisely,and the power losses calculation can be used as a basis of designing or selection to the gate driving power source.