Showing papers on "Integrated circuit published in 1977"

Analysis and Design of Analog Integrated Circuits

Abstract: The Fifth Edition of this academically rigorous text provides a comprehensive treatment of analog integrated circuit analysis and design starting from the basics and through current industrial practices. The authors combine bipolar, CMOS and BiCMOS analog integrated-circuit design into a unified treatment that stresses their commonalities and highlights their differences. The comprehensive coverage of the material will provide the student with valuable insights into the relative strengths and weaknesses of these important technologies.

CMOS analog integrated circuits based on weak inversion operations

Abstract: A simple model describing the DC behavior of MOS transistors operating in weak inversion is derived on the basis of previous publications. This model includes only two parameters and is suitable for circuit design. It is verified experimentally for both p- and n-channel test transistors of a Si-gate low-voltage CMOS technology. Various circuit configurations taking advantage of weak inversion operation are described and analyzed: two different current references based on known bipolar circuits, an amplitude detector scheme which is then applied to a quartz oscillator with the result of a very low-power consumption (<0.1 /spl mu/W at 32 kHz), and a low-frequency bandpass amplifier. All these circuits are insensitive to threshold and mobility variations, and compatible with a CMOS technology dedicated to digital low-power circuits.

Device Electronics for Integrated Circuits

Abstract: Semiconductor Electronics. Silicon Technology. Metal--Semiconductor Contacts. pn Junctions. Currents in pn Junctions. Bipolar Transistors I: Basic Properties. Bipolar Transistors II: Limitations and Models. Properties of the Metal--Oxide--Silicon System. Mos Field--Effect Transistors I: Physical Effects and Models. Mos Field--Effect Transistors II: High--Field Effects. Answers to Selected Problems. Selected List of Symbols. Index.

Operational Amplifiers and Linear Integrated Circuits

Abstract: 1. Introduction to Op-Amps. 2. First Experience with an Op-Amp. 3. Inverting and Noninverting Amps. 4. Comparators and Controls. 5. Selected Applications of Op-Amps. 6. Signal Generators. 7. Op-Amps with Diodes. 8. Differential, Instrumentation, and Bridge Amplifiers. 9. DC Performance: Bias, Offsets, and Drift. 10. AC Performance: Bandwidth, Slew Rate, Noise, and Frequency Compensation. 11. Active Filters. 12. Modulating and Frequency Changing with the Multiplier. 13. Integrated Circuit Timers. 14. D to A and A to D Converters. 15. Power Supplies. Answers. Index.

Thin film memory device employing amorphous semiconductor materials

Abstract: This disclosure relates to a thin film amorphous memory cell which can be fabricated upon the surface of a semiconductor substrate in such a manner as to minimize the surface area requirements for each cell thereby increase the packing density of the memory array Furthermore, since the cell can be fabricated on top of the semiconductor substrate, other active devices can be fabricated in the substrate so as to further increase the packing density of the integrated circuit chip containing memory array or other circuits The memory cell is formed of a thin film diode of one or more amorphous semiconductor layers that are doped to form either a PN junction diode or, with one such layer, a Schottky diode, and the memory cell includes an amorphous layer of a tellurium based chalcogenide material that may be employed in either a memory mode or a threshold mode so that the memory cell may be operated in either a non-volatile or volatile manner

Probe device for integrated circuit wafers

Abstract: A probe device for testing integrated circuit wafers is disclosed. The probe device comprises a support means, which has metallized portions, and an aperture. A plurality of "L" shaped holding means, each having a thin metallized surface, are coupled to metallized portions of the support means so that a portion of the holding means extends into the aperture. Coupled to the metallized surface of each of the holding means is a corresponding needle-like probe member which has a curved portion. These probe members are coupled to the holding means in such a manner that their curved portions extend into the support means aperture so as to electrically contact a circuit wafer placed therein, and thereby electrically couple the circuit wafer to the support means, and ultimately to circuit testing apparatus.

Plasma etching in integrated circuit manufacture—A review

Abstract: Plasma etching, the selective etching of material by reaction with chemically active radicals in a glow discharge, is dry and clean, and offers process simplification and improved dimensional tolerances compared to existing wet‐chemical‐etching processes in semiconductor integrated circuit (IC) device fabrication. In this paper previously published work on plasma etching and apparatus is reviewed, new processes and techniques for Al and Al–Si plasma etching and for the precise control of etchrates and detection of etchcycle endpoints are reported, and plasma etching and stripping are shown to be fully compatible with silicon gate, metal–oxide–semiconductor (MOS) device processing in a new ’’fully plasma‐etched ion‐implanted’’ 2‐μm channel‐length CMOS process. It is concluded that plasma etching and stripping technologies can have a significant impact on MOS manufacturing, in improving the tolerances and yield of conventional geometry devices with 4‐μm minimum linewidth, and in improving the resolution to ...

Integrated circuit connector

Abstract: A flexible printed circuit has printed electrical contacts which are spring loaded to corresponding integrated circuit contacts or to corresponding other circuit contacts to form a connector.

Potential of MOS Technologies for Analog Integrated Circuits

Abstract: Large-scale integrated circuits for many analog and combined analog-digital circuit functions are becoming feasible in N-channel and complementary metal-oxide-semiconductor technologies. Experimental results have been reported for analog to digital and digital to analog converters, a pulse-code-modulation voice encoder-decoder, and precision analog sampled-data frequency filters. Some of the key elements in these MOS circuits are precision-ratioed capacitor arrays, transistor analog switches, internally-compensated operational amplifiers, and offset-nulled comparators.

Dielectric Isolation: Comprehensive, Current and Future

Abstract: The continually increasing, widespread use of integrated circuits requires improved isolation techniques and characteristics beyond those obtainable with p‐n junctions. Junction isolated planar circuits have several limitations that dielectric isolation (DI) can substantially impact. For example, DI allows increased packing density, eliminates unwanted SCR action with the substrate (particularly important in cross points and radiation hardened devices), and provides higher collector‐base breakdown voltages. Unfortunately, such structures also have some limitations such as cost and manufacturing process problems. The advantages, problems, and future projections of DI circuit manufacturing are discussed following a review of the semiconductor industry's current DI processing technology.

Electronic multichip module

Abstract: An electronic multichip module suitable for use in a hostile environment. The module includes a metallic base member and a metallic cover hermetically and metallically sealed to the base member, the base member and cover together forming an enclosure. Spaced metallic support members are located within the enclosure and a plurality of integrated circuit units are stacked, in sandwich fashion, between the support members. The integrated circuit units each include a metal plate extending between the support members and an integrated circuit chip mounted thereon in heat conductive relationship. The metal plate, the support members and the enclosure form a heat sink for the integrated circuit units and the enclosure provides a low cost hermetic seal for the entire assembly of integrated circuit units. Planar arrays of conductive elements may be utilized to interconnect the integrated circuit chip to the terminals of the integrated circuit units. Means, such as pin connectors penetrating through the enclosure and attached conductors, provide electrical access to the terminals of the integrated circuit units within the enclosure.

Large-scale integration: what is yet to come?

Abstract: The rapid development of large-scale integrated circuits in the last two decades has revolutionized information handling. Higher levels of integration have been achieved principally by making the individual circuit elements smaller, but reduction of random defects and innovations in circuit design have also been important factors. Practical limits to the size of integrated circuits, such as those imposed by the use of photolithography to define the circuits, can be avoided by using other methods, such as solid-state diffusion or electron beams. The prospects are that dimensions and defect densities will continue to be reduced while speed increases. Redundancy in circuits will lead to lower costs and higher levels of integration. As logic becomes more complex and applications narrower, the increased number of unique circuit designs needed tends to increase costs. The microprocessor was developed to answer this problem and will have a radical influence on future computing systems.

The chip layout problem: an automatic wiring procedure

Abstract: This paper describes an automatic system for routing the metal connections on integrated circuit chips. The system contains three major sections: global wiring, vertical channel assignment, and horizontal bilateral channel allocation. Since its initial development in 1972, this system has been used successfully at IBM in the physical design of bipolar logic chips.

High-speed testing circuit

Abstract: High-speed testing circuitry which, when coupled to one terminal of a multi-terminal electronic device, such as an integrated circuit, can either supply test stimuli signals up to a frequency of 30 MHz, receive output signals produced by the device under test in response to test stimuli signals applied by associated test circuits and compare these signals against computer predicted signals, or provide for parametric testing of the device.

A practical introduction to electronic circuits

Abstract: Preface to third edition Preface to second edition Preface to first edition 1. Amplification and the transistor 2. The field-effect transistor 3. Thermionic valves and the cathode-ray tube 4. Negative feedback 5. Impedance matching 6. Semiconductor device characteristics 7. Amplification at high frequencies 8. Low-frequency signals, d.c. and the differential amplifier 9. Power supplies and power control 10. Pulse handling and time constants 11. Integrated circuit analogue building bricks 12. Positive feedback circuits and signal generators 13. Digital logic circuits 14. Microcomputer circuits and applications Appendix 1. Component identification Appendix 2. Transistor selection Appendix 3. Op amp data Appendix 4. Digital IC connections Appendix 5. Interfacing to the PC Bibliography Index.

Semiconductor integrated circuit device

Abstract: A semiconductor integrated circuit device having a construction of complementary PNP-NPN semiconductor devices in a monolithic integrated form. First and second N type epitaxial layers are formed on a common P type semiconductor substrate. A base region of the PNP transistor is produced by the diffusion of an impurity into the second epitaxial layer. The NPN transistor is formed as low emitter concentration type transistor and a part of the second epitaxial layer serves as the transmitter region of the NPN transistor.

The charge‐flow transistor: A new MOS device

Abstract: A new device, the charge‐flow transistor (CFT), has been developed to achieve integrated MOS compatibility in sensor applications, such as gas, humidity, and fire detection, where one is interested in monitoring the transverse resistance of a thin film. The resistive material is incorporated into the gate structure of the CFT in such a way that there is a time delay between the application of the gate‐to‐source voltage and the appearance of a complete channel. This time delay depends on the resistivity of the thin film. A theory of device operation is presented, together with experimental results on the first CFT’s. These results confirm the principles of operation, and demonstrate the utility of the CFT for making fully integrated sensing devices.

Tool for inserting and extracting integrated circuits

Abstract: A tool for handling integrated circuits to facilitate their installation on and extraction from circuit boards. A pair of spaced apart levers are pivotal about integral hinges in a manner to engage opposite ends of the integrated circuit. Each lever carries a pair of lugs between which the ends of the integrated circuit are gripped. The opposite end of the tool is constructed similarly although with a pair of levers that are closer together in order to handle a smaller integrated circuit.

High density printed circuit board and edge connector assembly

Abstract: A high density printed circuit board carrying integrated circuits or the like is provided with two parallel rows of terminals along one edge on both sides of the board. The terminals in the outer row of terminals closest to the edge of the board are connected to printed circuits on inner layers of the multiple layer printed circuit board by plated-through holes or other suitable techniques; and the printed circuits on the outer layer or layers are connected to the inner row of terminals spaced just inside the outer row of terminals. A circuit board connector is provided with spring contacts which are electrically insulated from one another but which are designed to engage the multiple layer printed circuit board at the position of the first and second rows of terminals. The spring contacts engaging the inner row of terminals on the circuit board are longer in length than those engaging the outer row of terminals, and are thus easily deflected so that the P.C. board may be inserted or removed from the connector without excessive force.

Integrated circuit package with optical input coupler

Abstract: A plastic encapsulated integrated circuit (IC) package is disclosed which includes a conical depression or dimple precisely located over a photo-responsive semiconductor element incorporated within said integrated circuit for performing a predetermined function. The IC is encapsulated in a clear, two-part epoxy moulding compound preferably Hysol MG-18 having a tapered small depression positioned to register with the photo element but stopping short of actually touching the semiconductor photo element. Thus, the bottom of the tapered depression consists of a transparent window of sufficient thickness to protect the semiconductor element and still provide optical coupling. The minimum diameter of the light input depression located preferably at the top of the clear plastic package is designed to receive a snug fitting light pipe of Lucite or other clear material that could be used as a fiber optic element. The light pipe can be retained in the IC depression by mechanical means or optionally it can be cemented in place. A suitable light source for activating the photo-responsive semiconductor element in the IC may be a light emitting diode or an incandescent lamp.

Electrical connector having a resilient cover

Abstract: An improved electrical connector is disclosed for mounting and electrically coupling an integrated circuit device to a circuit board. A resilient cover applies pressure at several points on a substrate on which the integrated circuit device is mounted to press the substrate against support surfaces in the connector base. Each of a plurality of flexible electrical contact elements extending from the support surfaces engages a corresponding conductive pad on the substrate with sufficient force to insure good electrical contact between the contact and the pad which is electrically coupled to the integrated circuit device by a conductive path on the substrate.

Gettering semiconductor wafers with a high energy laser beam

Abstract: A semiconductor wafer from which devices, such as transistors, integrated circuits or the like, are to be formed is gettered. This is done by directing a high energy beam, such as a laser beam, on the surface of the wafer opposite to the surface on which the devices are to be formed. The beam is absorbed by such surface and produces lattice damage and strain in the region of such surface. The wafer is then heated at a temperature and for a time sufficient to produce a dislocation array adjacent to the region of damage. This relieves the strain and attracts mobile defects in the wafer toward the array and away from the surface of the wafer on which the devices are to be formed. The beam may also be directed on the surface of the wafer where the semiconductor devices are to be formed so long as the beam avoids those portions of such surface where the devices are to be formed.

Semiconductor integrated circuit device

Abstract: A semiconductor integrated circuit device comprises at least a transistor comprising a semiconductor substrate including at least a single collector region of a first conductivity type, a plurality of base regions of a second conductivity type formed in the collector region, and emitter regions of the first conductivity type respectively formed in the base regions of the second conductivity type The second conductivity type base regions are electrically connected in common with one another and the first conductivity type emitter regions are electrically connected in common with one another A multilayer interconnection structure is employed so that the density of integration of the semiconductor integrated circuit device is high

Electrical properties of the Si–SiO2 interface and its influence on device performance and stability

Abstract: The two electrically active centers at the Si–SiO2 interface which can influence the performance and stability of MOSFET’s and bipolar transistors used in integrated circuits are interface traps and fixed charges. This paper is a brief review of the properties of interface traps and fixed charge, how these electrically active centers affect silicon device characteristics, and the largely empirical methods used to control the densities of these centers. These methods have been so successful that interface traps and fixed charge show no performance and stability problems in many types of integrated circuits.

Low power/high speed static ram

Abstract: An integrated circuit, metal-oxide-semiconductor (MOS) static random-access memory (RAM) with a power-down mode is described. The bistable memory cells employed in the memory include low conductivity, depletion mode transistors used as loads. "Zero" threshold voltage devices are employed on a low body-effect substrate to permit the powering-down of many circuits in the memory without affecting circuit performance. Several circuits employing these zero threshold devices are described.

Multi-level socket for an integrated circuit

Abstract: An integrated circuit socket adapted for use with circuits such as dual-in-line packages (DIPs) provides multilevel mounting for such integrated circuits. The socket body is formed to receive the first integrated circuit package while the second integrated circuit package is disposed above the first. Metallic contact members are disposed in holes arranged to coincide with the electrical leads subtending from each circuit. Each contact member is formed with means to receive the coincident electrical leads from the first and second circuits. Each contact member is formed to engage the socket preventing inadvertent removal of the contact member. The contact members are sufficiently long to extend through the socket and an associated printed circuit board to which they may be readily fixed by conventional means. In the one embodiment the socket is unitary and is formed with longitudinal protruding spacer members to separate it from the circuit board. In a second embodiment the socket is modular. Still a third embodiment provides an adjacent contact member allowing selective separate engagement of a lead from one of the two electronic packages.