Showing papers on "Ion implantation published in 1977"

Reordering of amorphous layers of Si implanted with 31P, 75As, and 11B ions

Abstract: The effect of impurities on the epitaxial regrowth of Si from amorphous layers created by ion implantation into 〈100〉 and 〈111〉 Si was studied by channeling effect measurements with 2‐MeV 4He ions. The Si wafers were first implanted at −180 °C with 28Si ions to form amorphous layers approximately 4000 A thick and then were implanted with 31P, 75As, or 11B ions to concentration levels of about 0.2–0.5 at.%. For these layers with impurity species the growth rate is found to be significantly higher than for those without. The measured regrowth rate at 500 °C for 〈100〉 Si with an impurity concentration of ∼2×1020 cm−3 of 31P or 75As is a factor of 6 greater, and of 11B a factor of 20 greater, than the regrowth rate in amorphous layers without impurities. For the case of 31P implanted 〈100〉 Si the activation energy of regrowth is close to that (2.35 eV) found for impurity‐free amorphous layers and for 11B implanted samples the energy is 1.9 eV. For 〈111〉 31P implanted Si specimens there is an increase in growth rate over that found in impurity‐free samples and a high level of residual disorder.

Influence of 16O, 12C, 14N, and noble gases on the crystallization of amorphous Si layers

Abstract: Channeling effect measurements have been used to study the effect of impurities on the epitaxial regrowth of amorphous silicon layers on single‐crystal silicon. Implantation was used to form the amorphous layers and also to introduce the impurities 12C, 14N, 16O, 20Ne, 40A, and 84Kr. For 16O implants, the growth rate at 550 °C depended on the 16O concentration and at the level of 0.5 at.% the rate was reduced from about 90 to about 10 A/min. For similar atomic concentrations of 14N, the rate was comparable to the 16O case. For comparable concentrations of 12C, the regrowth rate was found to be three times higher than for that of the 16O case. Noble gas ions are also found to retard the growth rate of the amorphous layers. For 40Ar at about the 0.5‐at.% level, the regrowth rate is appreciably slower than even that for the 16O case.

Dependence of residual damage on temperature during Ar+ sputter cleaning of silicon

Abstract: It has been found that the kind and amount of damage produced in silicon following Ar+ ion bombardment at 1.0 keV and the annealing properties of the damage depend strongly on the temperature at which the sputtering is done in the range 25–800 °C. Some of these differences in damage are not evident with surface‐sensitive techniques such as LEED, RHEED, or AES, but have been revealed by transmission electron microscopy and by Rutherford ion backscattering. TEM examination of substrates annealed at 800 °C after being sputtered at temperatures in the range 25–800 °C shows an increase in the density and the size of crystal defects with increasing sputtering temperature. Rutherford ion backscattering shows an increase in silicon disorder and in retained argon with increasing sputtering temperature. These results are similar to observations reported for ion implantation at higher energies. Models for damage mechanisms are discussed briefly. It is concluded that for Ar+ ion sputter cleaning of silicon, the silic...

Surface-layer composition changes in sputtered alloys and compounds

Abstract: Compositional changes of binary alloys and compounds have been observed (by Rutherford backscattering techniques) as a result of rare‐gas sputtering in the energy range 20–80 keV. After sputtering, the heavier components were generally found to be enriched in a surface layer whose thickness corresponded approximately to the range of the sputtering ion; the compositions of these enriched surface layers were independent of the mass and energy of the sputtering ions. This phenomenon of surface layer enrichment is interpreted as due to preferential sputtering from the surface in combination with defect‐enhanced diffusion.

Study of Encapsulants for Annealing GaAs

Abstract: Low temperature photoluminescence and Auger electron spectroscopy have been used to study chemical-vapor deposited SiO2 and SigN4 layers as en- capsulants for high temperature annealing of GaAs. Silicon dioxide or silicon oxynitride layers allow out-diffusion of Ga, while suitably prepared rf plasma deposited SisN4 layers can be used to anneal GaAs with negligible Ga out- diffusion. Ion implantation is a versatile method of doping semiconductors and is an established fabrication step for many silicon devices (1). Although the use of implantation in the III-V compounds is less wide- spread, important device applications have emerged. These include the fabrication of light emitting diodes (2), GaAs field-effect transistors, optical waveguid.es, and detectors (3). Because of the difficulties of selec- tively doping GaAs or other compound semiconductors by standard diffusion processes as compared with Si, it now appears that implantation will play an increas- ing role in future device applications of compound semiconductors. In view of the potential for this doping method, it is important to develop reliable procedures for im- plantation and annealing in these materials. Ion im- plantation produces considerable lattice damage which must be annealed out in order to restructure the lattice and activate the implanted impurities. While this pro- cedure is relatively straightforward in Si, annealing a compound semiconductor such as GaAs is more difficult. The incongruent evaporation of Ga and As from GaAs at temperatures ~ in excess of 600~ (4) makes it impossible to anneal bare GaAs samples without surface degradation. It is thus necessary to encapsulate the sample with a suitable dielectric layer or to perform the anneal in a carefully controlled ambient (5. 6). There have been numerous discussions of implantation and annealing in GaAs using encapsu- lants such as sputtered or chemical,vapor deposited SiO2 (7), thermally o r reactively deposited or sput- tered Si3N4 (8-10), or sputtered A1N (11). In the present work we have used low temperature photo- luminescence (PL) and Auger electron spectroscopy _(AES) to investigate the annealing-encapsulation properties of chemical vapor deposited SiO2 and rf plasma deposited Si.~N4 layers on GaAs. It is well known from diffusion experiments in Si that Ga has a very high diffusion coefficient in SiO2 (12). Gyulai et

Ion‐implanted n‐ and p‐type layers in InP

Abstract: InP has been doped by implantation with several different ions to yield layers of both n‐ and p‐type conductivity. Se+ and Si+ were found to be efficient n‐type dopants with activations in excess of 75% for moderate doses (1×1014 cm−2 at 400 keV). At doses of 1×1015 cm−2, sheet resistivities as low as 15 Ω/⧠ were obtained. Cd+, Mg+, and Be+ were all acceptors, with Mg+ yielding a sheet hole concentration as high as 5×1013 cm−2 for a dose of 1×1014 cm−2 at 150 keV. Reproducible annealing of implanted samples at temperatures up to 750 °C was accomplished with a pyrolytic phosphosilicate glass (PSG) encapsulation. Implants of Kr+ indicate that residual implantation damage is n type.

Some characteristics and uses of low‐pressure plasmas in materials science

Abstract: The preparation of stable thin films of controlled structure, composition, and thickness is a discipline bridging vacuum and materials sciences which has had significant effect on optics and electronics, although providing a limited number of working thin‐film substances. Techniques continue to be studied to extend the range of usable film materials on which thin‐film devices often depend for their development. Increasing use has been made in thin‐film technology of physical and chemical phenomena occurring in low‐pressure plasmas which are convenient in situ sources of activated gas and energetic ions to be applied as additional agents in film growth mechanisms. Thus ion extraction from plasmas for uniform doping during film growth is more likely to find wide use than ion implantation of solids. Energetic ions and/or activated species in ionized gas are now employed in processes for surface treatment (nitriding), deposition (sputtering, ’’ion plating,’’ activated evaporation, plasma polymerization), and ...

Blue electroluminescence from ZnSe diodes

Abstract: ZnSe p‐n junction diodes have been formed by nitrogen ion implantation. MIS diodes have also been made using a film of ZnSe oxidized in H2O2 solution for the insulator layer. Blue electroluminescence has been observed from both the diodes in forward bias at room temperature. The external quantum efficiency is about 10−5. The emission may originate from a bound exciton.

Trapping of hydrogen isotopes in molybdenum and niobium predamaged by ion implantation

Abstract: The trapping of hydrogen isotopes at defects in Mo and Nb have been studied. Ion beams of 11‐ and 18‐keV He+, 55‐keV O+ and Ne+, and 500‐keV Bi+ were used to create defects. Subsequently H or D was injected at room temperature by use of molecular beams of 16‐keV H+2 and D+2. Appreciable enhancements were observed in the amount of H and D retained within the near‐surface region of predamaged samples compared to samples with no prior damage. The total amount of D retained within the near‐surface region was measured by means of the nuclear reaction D(3He,p)4He, and H depth profiles were measured via a resonance in the nuclear reaction 1H(19F,αγ)16O. The H profiles correlate with the predicted predamaging ion profiles; however, appreciable tails to deeper depths for the hydrogen profiles are observed for the heavier predamaging ions. For a given predamage ion fluence, the amount of trapped deuterium increases linearly with incident deuterium fluence until a saturation in the enhancement is reached. The amount...

Dislocation networks in phosphorus-implanted silicon

Abstract: Observations, by transmission electron microscopy have been made on defects generated in 50 keV, high-dose (1 × 1015 to 3 × 1016 ions/em2) phosphorus-implanted silicon (111) wafers followed by 1100°C isothermal annealing in inert (dry N2) and oxidizing (wet O2) atmospheres. The formation of dislocation networks is closely associated with the generation of interstitial type dislocation loops which grow from point defects produced by ion implantation in silicon wafers. Also, dislocations grow more easily in wet O2 annealing than in dry N2. In wet O2 annealing, dislocation networks are formed by annealing within 1–2 min for samples implanted with doses above 3 × 1015 ions/cm2, and they move to deeper depths in the wafers during annealing. On the other hand, in dry N2 annealing, the critical ion dose for generation of dislocation networks is 1 × 1016 ions/cm2 and the location of dislocation networks in the wafers is usually unchanged during annealing. Such a difference in the generation and motion of...

Stress in ion‐implanted CVD Si3N4 films

Abstract: The compressive stress buildup caused in chemical‐vapor‐deposited (CVD) Si3N4 films by ion implantation is shown to be caused entirely by atomic collision effects, ionization effects being unimportant. The stress introduction rate is shown to be independent of CVD processing variables and O content of the film. The maximum attainable compressive stress change is 3.5×1010 dyn/cm2, resulting in a maximum net compressive stress of 2×1010 dyn/cm2 for films on Si where the as‐deposited films inherently have 1.5×1010 dyn/cm2 tensile stress before ion implantation. Results are presented which show that O in the films inhibits thermal annealing of the ion‐implantation‐induced compressive stress. Results for introduction rate and annealing effects are presented in normalized form so that workers can use the effects for intentional stress level adjustment in the films to reduce probability of cracking and detachment.

On the shrinkage of rod‐shaped defects in boron‐ion‐implanted silicon

Abstract: Three different types of rod‐shaped defects formed during postimplantation annealing of boron‐implanted silicon are distinguished in annealing experiments carried out on transmission electron microscope specimens It is shown that rod‐shaped defects can be boron precipitates, Frank dipoles, or perfect a/2 <110≳ dipoles All shrink from the ends only during annealing The temperature dependence of shrinkage rate for the first type was determined by measuring dL/dt at three different temperatures for a given isolated defect Boron diffusion appeared to be the rate‐determining process The second type, Frank dipoles, were often observed to unfault, transforming into the third type during annealing At the time of unfaulting the newly formed perfect dipole was always observed to rotate on its glide cylinder to near edge orientation

Arsenic implantation into polycrystalline silicon and diffusion to silicon substrate

Abstract: Arsenic implantation into polycrystalline silicon and drive‐in diffusion to silicon substrate have been investigated by MeV He+ backscattering analysis and also by electrical measurements. The range distributions of arsenic implanted into polycrystalline silicon are well fitted to Gaussian distributions over the energy range 60–350 keV. The measured values of RP and ΔRP are about 10 and 20% larger than the theoretical predictions, respectively. The effective diffusion coefficient of arsenic implanted into polycrystalline silicon is expressed as D=0.63 exp[(−3.22 eV/kT)] and is independent of the arsenic concentration. The drive‐in diffusion of arsenic from the implanted polycrystalline silicon layer into the silicon substrate is significantly affected by the diffusion atmosphere. In the N2 atmosphere, a considerable amount of arsenic atoms diffuses outward to the ambient. The outdiffusion can be suppressed by encapsulation with Si3N4. In the oxidizing atmosphere, arsenic atoms are driven inward by growing...

Effects of dislocations in silicon transistors with implanted emitters

Abstract: Silicon bipolar transistors have been made by substituting a shallow phosphorus implanation for the standard emitter deposition used in the manufacture of linear integrated circuits. The implantation was followed by a high temperature heat treatment (drive-in), which caused the implanted ions to diffuse deeper into the semiconductor to give emitter/base junction depths of typically 1.8 μm. When the high temperature heat treatment was performed in an oxidising atmosphere, the resulting transistors had lower gains and higher emitter/base leakages than the comparable standard diffused transistors. However, if an 1180°C drive-in, in an inert atmosphere, was performed prior to the oxidation drive-in, high gains and low emitter/base leakages were obtained. Alternatively, if the oxidation drive-in was omitted, and instead an inert drive-in performed at any temperature between 1000 and 1180°C, high gains and low emitter/base leakages were again obtained. Etching and TEM studies revealed that the low gains and high emitter/base leakages were again obtained. Etching and TEM studies revealed that the low gains and high emitter/base leakages were caused by emitter edge dislocations intersection the emitter/base junction around the perimeter of the emitter. A mechanism is suggested to describe the formation of the emitter edge dislocations.

Ion implantation as an ultrafast quenching technique for metastable alloy production: The Ag‐Cu system

Abstract: Substitutional solid solutions of Ag in Cu have been formed by ion implanting Ag at concentrations up to 16 at.%. The physical states of the implanted alloys were deduced by ion channeling and transmission electron microscopy and their stability was examined by annealing to 400 °C. The implantation results are compared with those obtained previously by conventional rapid quenching techniques.

Method of semiconductor solar energy device fabrication

Abstract: This disclosure relates to a semiconductor solar energy device which is of the PN-type and utilizes a dielectric anti-reflective coating on the side of the device that faces the sunlight. The fabrication techniques used in making this semiconductor device include the use of a rough or textured pyramid shaped silicon surface beneath the anti-reflective coating to increase solar cell efficiency. Also, ion implantation is used to form the PN junction in the device. The ion implanted region located on the side of the device that is subjected to the sunlight is configured in order to permit metal ohmic contact to be made thereto without shorting through the doped region during sintering of the metal contacts to the semiconductor substrate. The dielectric anti-reflective coating, in one embodiment, is a composite of silicon dioxide and silicon nitride layers. The device is designed to permit solder contacts to be made to the P and N regions thereof without possibility of shorting to semiconductor regions of opposite type conductivity.

Amorphous-polycrystal transition induced by laser pulse in self-ion implanted silicon

Abstract: Reflection high energy electron diffraction has been used to investigate the amorphous to polycrystalline structure transition in silicon induced by laser pulse. The power density of the ruby laser pulse, in the free generation mode, has been maintained below the threshold to induce surface damage. Depth analysis has been carried out in 〈100〉 silicon crystal using the channeling effect technique.

Silicon solar cells by high-speed low-temperature processing

Abstract: A new method for silicon solar cell fabrication is being developed around ion implantation and pulsed electron beam techniques. Cells are fabricated totally in a vacuum environment at room temperature. Major reductions result in the time, energy consumption, and waste material generation associated with solar cell production. Cells to date have exhibited air mass zero efficiencies exceeding 10 percent.

Method of fabricating silicon photodiodes

Abstract: METHOD OF FABRICATING SILICON PHOTODIODES Abstract of the Disclosure Described is a method of fabricating front-illuminated silicon photodiodes having high quantum efficiency, a short response time, (high gain and low excess noise in the case of avalanche diodes), low dark currents and good reliability. In the fabrication of an n+-p-.pi.-p+ APD the method includes the steps of: (1) epitaxially growing a high resistivity .pi.-type silicon layer on a high conduc-tivity p-type silicon substrate; (2) forming an n-type guard ring in the .pi.-layer; (3) forming a p-type channel stop around the guard ring; (4) forming in the .pi.-layer a p-layer by ion implantation and by driving in the implanted ions by heating in a suitable atmosphere; (5) masking the p-layer and introducing phosphorus into the backside to getter defects and/or impurities; (6) ramping the furnace temperature during steps (2) through (5) to reduce crystalline defects; (7) forming a thin n+-layer in the p-layer; (8) forming an anti-reflection and passivation coating on the n+-layer; and (9) forming electrical contacts to the substrate, the guard ring and the channel stop so that the latter two contacts overlap the surface portions of the corresponding metallurgical junctions. The n+-layer is made extremely thin in order to reduce hole injection caused by light incident on that layer, and the ion implantation - drive step (4) and subsequent steps which involve heating are mutually adapted so that the resultant electric field profile in the multiplication region (p-layer) is substantially triangular. A similar process, which omits step (4), is also described for the fabrication of n+-.pi.-p+ photodiodes.

Ion Implantation in semiconductors, 1976

Abstract: Separate abstracts have been prepared for items within the scope of the energy data base. (FS)

The Identification of the Mobile Ion during the Anodic Oxidation of Silicon

Abstract: The mobile species during anodic oxidation of Si is shown to be largely, if not entirely, the anion. This was accomplished by introducing noble gases as markers into the surface layer of specimens by ion implantation. The positions of the markers before and after oxidation in a variety of electrolytes were determined by Rutherford backscattering analysis.

MOS Hardening Approaches for Low-Temperature Applications

Abstract: Charge buildup in irradiated MOS devices is significantly more severe at low temperatures than at room temperature. Approaches for counteracting this problem are considered in this paper, including: (1) careful selection of the applied field; (2) ion implantation of the oxide; (3) use of a thin oxide. Experimental and analytical results are presented and it is demonstrated that the applied field dependence of flatband voltage shift in MOS capacitors irradiated at 77°K can be accounted for in terms of the field dependence of electron yield and the transport of holes at high fields. Analysis of ion implantation effects indicates that a significant improvement in radiation tolerance should be achievable by this method. A simultaneous consideration of the effects of oxide thickness and applied field on charge buildup in an unimplanted oxide suggests that reducing the thickness to ?500 A° will largely eliminate low temperature problems in a steady-state ionizing radiation environment as long as the applied voltage is ? 10V.

Schottky-gate field-effect transistor and fabrication process therefor

Abstract: The specification describes a Schottky-gate field-effect transistor and related fabrication process wherein thin ion implanted surface stabilization regions are formed between source and gate electrodes and gate and drain electrodes of the device and to a thickness of between 100 and 1,000 angstroms. This is accomplished utilizing the source, gate and drain electrodes as an ion implantation mask against impinging inert ions which render the implanted regions semi-insulating, and this process requires no post-implantation annealing.

Ion Implanted N-Type Contact for High-Purity Germanium Radiation Detectors

Abstract: Thin large-area n+ contacts on high-purity germanium detectors have been produced by implantation of 25 keV phosphorous ions. The contacts show leakage current of 2000 V/cm. Unannealed lattice damage may still limit the maximum applied field, but proper surface treatment prior to implantation and subsequent annealing steps have resulted in a dramatic improvement in the applied field. Spectra are presented which demonstrate that the n+ window is thin and the spectrometer performance is excellent.

High fluence deuteron bombardmemnt of silicon

Abstract: A study has been made of d+ ion implantation in Si(111) at 100 K and 300 K. Deuterium depth profiles as a function of fluence were obtained using a method based on observing the energy spectra of the tritons and protons from the D(d, p)T reaction induced with a deuteron beam. Profiles at 300 K show two distinct regions in the target. For a fluence of 4 × 1015 d+/cm2 the surface region which extends over the first half of the deuteron range contains little deuterium (∼ 0.3 atomic %) while a relatively large amount (∼ 5 at. %) is retained in a buried layer. Typical scanning electron micrographs taken following implantation are presented. They show the deeper layers to be highly damaged. In striking contrast, the surface region shows little observable damage even for doses exceeding 1019d+/cm2. Deuterium diffusion coefficients are estimated for silicon under irradiation conditions.

Method for forming ion-implanted self-aligned gate structure by controlled ion scattering

Abstract: A method of manufacturing a silicon gate MIS device using ion implantation and controlled ion scattering to provide concurrent formation and automatic alignment of the gate structure and adjacent impurity regions. In a preferred embodiment, the process is for the gate structure and source and drain of silicon gate FETs. The layered gate constituents--typically oxide and silicon--are formed on a semiconductor wafer. A photoresist mask which is larger than the desired gate size is formed on the silicon and the silicon is etched to the predetermined gate size beneath the overhanging mask. The photoresist mask is then used during ion implantation of the source and drain to establish the lateral surface boundaries within which ions are implanted. These lateral surface boundaries are selected so that as the ions are driven into the substrate to the desired junction depth of the source and drain by lateral scattering, the source and drain are aligned with the silicon gate electrode.

Semiconductor lifetime measurement method

Abstract: A method for the measurement of minority carrier lifetime in semiconductor wafers, sheets and ribbons by purely optical means. The method does not require electrical or MOS contacts to the wafer, nor does it require any specific processing to facilitate measurement. The technique is non-destructive, and is applicable to any semiconductor wafer, with or without surface dielectric films (e.g., SiO 2 , Si 3 N 4 , Ta 2 O 5 ) as long as it has no metal films. This technique is fast, accurate, and of reasonable high resolution, so that it may be applied to evaluate the effects of specific process steps (e.g., ribbon growth, diffusion, oxidation, ion implantation, delectric deposition, annealing) in real time and hence serve as a production control technique as well as a research tool. By utilizing reasonable equipment sophistication, this technique should enable the measurement of lifetime over a wide range of values, covering the scale from high-speed bipolar devices and integrated circuits (˜10 -9 s) to power transistors and solar cells (˜10 -3 s).

Ion implantation apparatus with a cooled structure controlling the surface potential of a target surface

Abstract: In an ion beam apparatus a structure for controlling the surface potential of the target comprising an electron source adjacent to the beam for providing electrons to the beam and means between the target and source for inhibiting rectilinear radiations, i.e., electron and other particle and photon radiations between said source and said target. This prevents heating of the target by the electron source and cross-contamination between the source and the target. The apparatus further includes means for maintaining said shield means at a lower temperature than said target. A further structure is provided for the measurement of the ion beam current while controlling said surface potential of the target which includes: walls adjacent to and electrically insulated from the target and surrounding the beam whereby the walls and target provide a Faraday Cage, means for introducing variable quantities of electrons into the beam within the Faraday Cage, means for measuring the target current, means for combining and measuring the target and wall currents to provide said ion beam current measurement and means for varying the quantities of introduced electrons to control the target current and thereby the target surface potential. Likewise, this apparatus further includes means for maintaining said shielding means at a temperature lower than said target.

Ion implanted Schottky barrier diode

Abstract: A Schottky barrier diode having a subsurface metalsemiconductor rectifying barrier with electrical rectification properties immune to semiconductor surface contamination. A special ion implantation technique is used to produce a very thin but strongly metallic island-like region in a semiconductive body. A Schottky barrier separates the region from the semiconductive body below the semiconductor body surface. A special truncated Gaussian profile in metal concentration through the thickness of the region provides low thermal and electrical resistance between the Schottky barrier and the region surface.