Showing papers on "Latency (engineering) published in 2010"

Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing

Abstract: Phase Change Memory (PCM) is emerging as a promising technology to build large-scale main memory systems in a cost-effective manner. A characteristic of PCM is that it has write latency much higher than read latency. A higher write latency can typically be tolerated using buffers. However, once a write request is scheduled for service to a bank, it can still cause increased latency for later arriving read requests to the same bank. We show that for the baseline PCM system with read-priority scheduling, the write requests increase the effective read latency to 2.3x (on average), causing significant performance degradation. To reduce the read latency of PCM devices under such scenarios, we propose adaptive Write Cancellation policies. Such policies can abort the processing of a scheduled write requests if a read request arrives to the same bank within a predetermined period. We also propose Write Pausing, which exploits the iterative write algorithms used in PCM to pause at the end of each write iteration to service any pending reads. For the baseline system, the proposed technique removes 75% of the latency increase incurred by read requests and improves overall system performance by 46% (on average), while requiring negligible hardware and simple extensions to PCM controller.

MEG detection of delayed auditory evoked responses in autism spectrum disorders: towards an imaging biomarker for autism.

Abstract: Motivated by auditory and speech deficits in autism spectrum disorders (ASD), the frequency dependence of superior temporal gyrus (STG) 50 msec (M50) and 100 msec (M100) neuromagnetic auditory evoked field responses in children with ASD and typically developing controls were evaluated. Whole-cortex magnetoencephalography (MEG) was obtained from 17 typically developing children and 25 children with ASD. Subjects were presented tones with frequencies of 200, 300, 500, and 1,000 Hz, and left and right STG M50 and M100 STG activity was examined. No M50 latency or amplitude Group differences were observed. In the right hemisphere, a Group × Frequency ANOVA on M100 latency produced a main effect for Group (P 5 0.01), with an average M100 latency delay of 11 msec in children with ASD. In addition, only in the control group was the expected association of earlier M100 latencies in older than younger children observed. Group latency differences remained significant when hierarchical regression analyses partialed out M100 variance associated with age, IQ, and language ability (all P-values < 0.05). Examining the right-hemisphere 500 Hz condition (where the largest latency differences were observed), a sensitivity of 75%, a specificity of 81%, and a positive predictive value (PPV) of 86% was obtained at a threshold of 116 msec. The M100 latency delay indicates disruption of encoding simple sensory information. Given similar findings in language impaired and nonlanguage impaired ASD subjects, a right-hemisphere M100 latency delay appears to be an electrophysiological endophenotype for autism.

The Gemini System Interconnect

Abstract: The Gemini System Interconnect is a new network for Cray’s supercomputer systems. It provides improved network functionality, latency and issue rate. Latency is reduced with OS bypass for sends and direct user completion notification on receives. Atomic memory operations support the construction of fast synchronization and reduction primitives.

Low latency cacheable media streaming

Abstract: A low latency streaming system provides a stateless protocol between a client and server with reduced latency. The server embeds incremental information in media fragments that eliminates the usage of a typical control channel. In addition, the server provides uniform media fragment responses to media fragment requests, thereby allowing existing Internet cache infrastructure to cache streaming media data. Each fragment has a distinguished Uniform Resource Locator (URL) that allows the fragment to be identified and cached by both Internet cache servers and the client's browser cache. The system reduces latency using various techniques, such as sending fragments that contain less than a full group of pictures (GOP), encoding media without dependencies on subsequent frames, and by allowing clients to request subsequent frames with only information about previous frames.

Towards an Understanding of the Herpes Simplex Virus Type 1 Latency-Reactivation Cycle

Abstract: Infection by herpes simplex virus type 1 (HSV-1) can cause clinical symptoms in the peripheral and central nervous system. Recurrent ocular shedding can lead to corneal scarring and vision loss making HSV-1 a leading cause of corneal blindness due to an infectious agent. The primary site of HSV-1 latency is sensory neurons within trigeminal ganglia. Periodically, reactivation from latency occurs resulting in virus transmission and recurrent disease. During latency, the latency-associated transcript (LAT) is abundantly expressed. LAT expression is important for the latency-reactivation cycle in animal models, in part, because it inhibits apoptosis, viral gene expression, and productive infection. A novel transcript within LAT coding sequences (AL3) and small nonprotein coding RNAs are also expressed in trigeminal ganglia of latently infected mice. In this review, an update of viral factors that are expressed during latency and their potential roles in regulating the latency-reactivation cycle is discussed.

Addressing burstiness for reliable communication and latency bound generation in wireless sensor networks

Abstract: As wireless sensor networks mature, they are increasingly being used in real-time applications. Many of these applications require reliable transmission within latency bounds. Achieving this goal is very difficult because of link burstiness and interference. Based on significant empirical evidence of 21 days and over 3,600,000 packets transmission per link, we propose a scheduling algorithm that produces latency bounds of the real-time periodic streams and accounts for both link bursts and interference. The solution is achieved through the definition of a new metric Bmax that characterizes links by their maximum burst length, and by choosing a novel least-burst-route that minimizes the sum of worst case burst lengths over all links in the route. A testbed evaluation consisting of 48 nodes spread across a floor of a building shows that we obtain 100% reliable packet delivery within derived latency bounds. We also demonstrate how performance deteriorates and discuss its implications for wireless networks with insufficient high quality links.

Short Communication Analysis of latent viral gene expression in natural and experimental latency models of human cytomegalovirus and its correlation with histone modifications at a latent promoter

Abstract: Human cytomegalovirus (HCMV) is an opportunistic human pathogen that establishes a lifelong latent infection, which can reactivate periodically. If unchecked by a robust immune response, this reactivation can result in severe disease in immunocompromised patients. Reactivation of latent virus in myeloid progenitor cells is concomitant with cellular differentiation through regulation of the major immediate-early promoter (MIEP) by chromatin remodelling. In this study, we analysed the expression of the latent gene transcript UL81-82as (LUNA). LUNA is expressed in latently infected CD34(+) cells and its expression decreases as CD34(+) cells differentiate to immature dendritic cells. Upon maturation (and HCMV reactivation), a second wave of transcription occurs, consistent with expression during lytic infection. Furthermore, we show that the LUNA promoter is associated with acetylated histones during HCMV latency in experimentally and naturally infected CD34(+) cells, thus suggesting that latent gene promoters are, like the MIEP, regulated by post-translational modifications of their associated histone proteins.

Mechanisms of HIV Latency: an Emerging Picture of Complexity

Abstract: Rarely HIV type 1 establishes proviral latency within the host genome, maintained with little or no viral gene expression. This state has been quantitated in peripheral blood and lymphoid tissues of HIV-infected patients, appearing in the earliest days of infection. These rare cellular reservoirs are unaffected by current antiretroviral therapy and unrecognized by the host immune response, and can regenerate disseminated viremia if therapy is interrupted. Proviral latency may be established when a newly HIV-infected cell exits the cell cycle and returns to the resting state. Rarely, direct infection of resting cells may also occur. Multiple molecular mechanisms appear to underlie the establishment and maintenance of persistent, latent HIV infection, most frequent in the resting central memory CD4+ T cell. Interrupting processes that maintain latency may allow therapeutic attack of this primary form of persistent HIV infection, but a better understanding of relevant mechanisms in vivo is needed.

Systems and methods of measuring latency and routing thereon in optical networks

Abstract: The present disclosure provides systems and methods for making latency measurements and using these measurements in routing in optical networks. In an exemplary embodiment, a method is defined whereby two nodes sharing a line automatically determine whether both nodes are capable of making a latency measurement and then which node will initiate and which node participates in making the latency measurement. In another exemplary embodiment, an on-demand latency measurement may be made between any two arbitrary nodes within a domain. Routing messages may be used to disseminate the latency of links via a signaling and routing protocol. Advantageously, the present invention provides measurement of latency and latency variation of customer circuits (i.e., SNCs) using an in-band, non-intrusive calculation with a high-degree of accuracy. Furthermore, the present invention may consider these calculations for circuit routing based on the latency and circuit acceptance based on maximum latency restrictions.

Dynamic latency-based rerouting

Abstract: A switch creates and dynamically updates a latency map of a network to adjust routing of flows. Further, the network is monitored to detect latency issues and trigger a dynamic adjustment of routing based on the latency map. In this manner, a flow can be routed along a route (i.e., a faster route) that provides less latency than other available routes. The latency map can be generated based on latency probe packets that are issued from and returned to the source switch. By evaluating many such latent probe packets that have traveled along many available routes (e.g., corresponding to various ports of the switch), the switch or associated administrative logic can dynamically adjust the latency map to updated latency information of available routes. Therefore, responsive to a trigger, the source switch can dynamically adjust the routing of a flow based on latency issues discerned from the network.

Schedulability Analysis for Real Time On-Chip Communication with Wormhole Switching

Abstract: In this paper, the authors discuss a real-time on-chip communication service with a priority-based wormhole switching policy. The authors present a novel off-line schedulability analysis approach, worst case network latency analysis. By evaluating diverse inter-relationships and service attributes among the traffic flows, this approach can predict the packet network latency for all practical situations. The simulation results provide evidence that communication latency calculated using the real time analysis approach is safe, closely matching the figures obtained from simulation.

MaxMAC: a maximally traffic-adaptive MAC protocol for wireless sensor networks

Abstract: Energy efficiency is a major concern in the design of Wireless Sensor Networks (WSNs) and their communication protocols. As the radio transceiver typically accounts for a major portion of a WSN node’s power consumption, researchers have proposed Energy-Efficient Medium Access (E2-MAC) protocols that switch the radio transceiver off for a major part of the time. Such protocols typically trade off energy-efficiency versus classical quality of service parameters (throughput, latency, reliability). Today’s E2-MAC protocols are able to deliver little amounts of data with a low energy footprint, but introduce severe restrictions with respect to throughput and latency. Regrettably, they yet fail to adapt to varying traffic load at run-time. This paper presents MaxMAC, an E2-MAC protocol that targets at achieving maximal adaptivity with respect to throughput and latency. By adaptively tuning essential parameters at run-time, the protocol reaches the throughput and latency of energy-unconstrained CSMA in high-traffic phases, while still exhibiting a high energy-efficiency in periods of sparse traffic. The paper compares the protocol against a selection of today’s E2-MAC protocols and evaluates its advantages and drawbacks.

Method and apparatus for adaptive transmission of sensor data with latency controls

Abstract: Disclosed is a method and apparatus to continuously transmit high bandwidth, real-time data, on a communications network (e.g., wired, wireless, and a combination of wired and wireless segments). A control computing device uses user or application requirements to dynamically adjust the throughput of the system to match the bandwidth of the communications network being used, so that data latency is minimized. An operator can visualize the instantaneous characteristic of the link and, if necessary, make a tradeoff between the latency and resolution of the data to help maintain the real-time nature of the system and better utilize the available network resources. Automated control strategies have also been implemented into the system to enable dynamic adjustments of the system throughput to minimize latency while maximizing data resolution. Several applications have been cited in which latency minimization techniques can be employed for enhanced dynamic performance.

Analyzing MAC protocols for low data-rate applications

Abstract: The fundamental WSN requirement to be energy-efficient has produced a whole range of specialized Medium Access Control (MAC) protocols. They differ in how performance (latency, throughput) is trade...

Interferon Alpha Induces Establishment of Alphaherpesvirus Latency in Sensory Neurons In Vitro

Abstract: Background: Several alphaherpesviruses, including herpes simplex virus 1 (HSV-1) and pseudorabies virus (PRV), establish lifelong latency in neurons of the trigeminal ganglion (TG). Although it is thought that efficient establishment of alphaherpesvirus latency is based on a subtle interplay between virus, neurons and the immune system, it is not clear which immune components are of major importance for the establishment of latency. Methodology/Principal Findings: Here, using an in vitro model that enables a natural route of infection, we show that interferon alpha (IFNalpha) has the previously uncharacterized capacity to induce a quiescent HSV-1 and PRV infection in porcine TG neurons that shows strong similarity to in vivo latency. IFNalpha induced a stably suppressed HSV-1 and PRV infection in TG neurons in vitro. Subsequent treatment of neurons containing stably suppressed virus with forskolin resulted in reactivation of both viruses. HSV and PRV latency in vivo is often accompanied by the expression of latency associated transcripts (LATs). Infection of TG neurons with an HSV-1 mutant expressing LacZ under control of the LAT promoter showed activation of the LAT promoter and RT-PCR analysis confirmed that both HSV-1 and PRV express LATs during latency in vitro. Conclusions/Significance: These data represent a unique in vitro model of alphaherpesvirus latency and indicate that IFNalpha may be a driving force in promoting efficient latency establishment.

Apparatus and methods for identifying and characterizing latency in a content delivery network

Abstract: Methods and apparatus for identification and characterization of latency in a content delivery network. In one embodiment, interaction of users with content is recorded via the collection of a plurality of tuning records; the latency is then utilize to adjust the timing on the tuning records to account for lapses in time for sending these from between entities of the network and the user devices, and for processing occurring at the devices as required. The latency is determined by taking into account an experimentally or manufacturer-derived device specific latency component, and a network latency component. The network latency component is determined in one variant by sending a message to the device from the network requesting a current system time (or other response). Once the timing of the tuning records is adjusted, these tuning records may be relied upon as being accurate representations of subscriber interaction with content on a second-by-second basis. Accordingly, tuning records may be obtained and analyzed for content which lasts for very short periods of time (e.g. advertisements).

Back Suction: Service Guarantees for Latency-Sensitive On-chip Networks

Abstract: Networks-on-chip for future many-core processor platforms face an increasing diversity of traffic requirements, ranging from streaming traffic with real-time requirements to bursty latency-sensitive best-effort traffic from general-purpose processors with caches. In this paper, we propose Back Suction, a novel flow-control scheme to implement quality-of-service. Traffic with service guarantees is selectively prioritized upon low buffer occupancy of downstream routers. As a result, best-effort traffic is preferred for an improved latency as long as guaranteed service traffic makes sufficient progress. We present a formal analysis and an experimental evaluation of the Back Suction scheme showing improved latency of best effort traffic when compared to current approaches even under formal service guarantees for streaming traffic.

Network page latency reduction using gamma distribution

Abstract: Disclosed are various embodiments of a system, method and computer readable medium for network page latency reduction. In one embodiment, among others, a system comprises a processor circuit and a memory associated with the processor circuit. The system further comprises a distribution estimator configured to estimate a distribution corresponding to latency data regarding a plurality of instances of a network page. The system further comprises an attribute comparator configured to identify an attribute associated with a subset of the instances of a network page. The subset of the instances corresponds to a latency data substantially represented by a tail of the distribution. Additionally, the system comprises a recommendation generator configured to generate a modification recommendation for the subset of the instances of the network page.

Not all microseconds are equal: fine-grained per-flow measurements with reference latency interpolation

Abstract: New applications such as algorithmic trading and high-performance computing require extremely low latency (in microseconds). Network operators today lack sufficient fine-grain measurement tools to detect, localize and repair performance anomalies and delay spikes that cause application SLA violations. A recently proposed solution called LDA provides a scalable way to obtain latency, but only provides aggregate measurements. However, debugging application-specific problems requires per-flow measurements, since different flows may exhibit significantly different characteristics even when they are traversing the same link. To enable fine-grained per-flow measurements in routers, we propose a new scalable architecture called reference latency interpolation (RLI) that is based on our observation that packets potentially belonging to different flows that are closely spaced to each other exhibit similar delay properties. In our evaluation using simulations over real traces, we show that RLI achieves a median relative error of 12% and one to two orders of magnitude higher accuracy than previous per-flow measurement solutions with small overhead.

The role of latency in the validity of AR simulation

Abstract: It is extremely challenging to run controlled studies comparing multiple Augmented Reality (AR) systems. We use an AR simulation approach, in which a Virtual Reality (VR) system is used to simulate multiple AR systems. To investigate the validity of this approach, in our first experiment we carefully replicated a well-known study by Ellis et al. using our simulator, obtaining comparable results. We include a discussion on general issues we encountered with replicating a prior study. In our second experiment further exploring the validity of AR simulation, we investigated the effects of simulator latency on the results from experiments conducted in an AR simulator. We found simulator latency to have a significant effect on 3D tracing, however there was no interaction between simulator latency and artificial latency. Based on the results from these two experiments, we conclude that simulator latency is not inconsequential in determining task performance. Simulating visual registration is not sufficient to simulate the overall perception of registration errors in an AR system. We also need to keep simulator latency at a minimum. We discuss the impact of these results on the use of the AR simulation approach.

Exploiting Concurrency to Improve Latency and throughput in a Hybrid Storage System

Abstract: This paper considers the problem of how to improve the performance of hybrid storage system employing solid state disks and hard disk drives. We utilize both initial block allocation as well as migration to reach “Wardrop equilibrium”, in which the response times of different devices equalize. We show that such a policy allows adaptive load balancing across devices of different performance. We also show that such a policy exploits parallelism in the storage system effectively to improve throughput and latency simultaneously. We implemented a prototype in Linux and evaluated it in multiple workloads and multiple configurations. The results show that the proposed approach improved both the latency of requests and the throughput significantly, and it adapted to different configurations of the system under different workloads.

Effects of Packet Loss and Latency on the Temporal Discrimination of Visual-Haptic Events

Abstract: Temporal discontinuities and delay caused by packet loss or communication latency often occur in multimodal telepresence systems. It is known that such artifacts can influence the feeling of presence [1]. However, it is largely unknown how the packet loss and communication latency affect the temporal perception of multisensory events. In this article, we simulated random packet dropouts and communication latency in the visual modality and investigated the effects on the temporal discrimination of visual-haptic collisions. Our results demonstrated that the synchronous perception of crossmodal events was very sensitive to the packet loss rate. The packet loss caused the impression of time delay and influenced the perception of the subsequent events. The perceived time of the visual event increased linearly, and the temporal discrimination deteriorated, with increasing packet loss rate. The perceived time was also influenced by the communication delay, which caused time to be slightly overestimated.

Use of a Virus-Encoded Enzymatic Marker Reveals that a Stable Fraction of Memory B Cells Expresses Latency-Associated Nuclear Antigen throughout Chronic Gammaherpesvirus Infection

Abstract: An integral feature of gammaherpesvirus infections is the ability to establish lifelong latency in B cells. During latency, the viral genome is maintained as an extrachomosomal episome, with stable maintenance in dividing cells mediated by the viral proteins Epstein-Barr nuclear antigen 1 (EBNA-1) for Epstein-Barr virus and latency-associated nuclear antigen (LANA) for Kaposi9s sarcoma-associated herpesvirus. It is believed that the expression of episome maintenance proteins is turned off in the predominant long-term latency reservoir of resting memory B cells, suggesting that chronic gammaherpesvirus infection is primarily dormant. However, the kinetics of LANA/EBNA-1 expression in individual B-cell subsets throughout a course of infection has not been examined. The infection of mice with murine gammaherpesvirus 68 (MHV68, γHV68) provides a model to determine the specific cellular and molecular events that occur in vivo during lifelong gammaherpesvirus latency. In work described here, we make use of a heterologously expressed enzymatic marker to define the types of B cells that express the LANA homolog (mLANA) during chronic MHV68 infection. Our data demonstrate that mLANA is expressed in a stable fraction of B cells throughout chronic infection, with a prominent peak at 28 days. The expression of mLANA was detected in naive follicular B cells, germinal-center B cells, and memory B cells throughout infection, with germinal-center and memory B cells accounting for more than 80% of the mLANA-expressing cells during the maintenance phase of latency. These findings suggest that the maintenance phase of latency is an active process that involves the ongoing proliferation or reseeding of latently infected memory B cells.

Energy- and Latency-Efficient Processing of Full-Text Searches on a Wireless Broadcast Stream

Abstract: In wireless mobile computing environments, broadcasting is an effective and scalable technique to disseminate information to a massive number of clients, wherein the energy usage and latency are considered major concerns. This paper presents an indexing scheme for the energy- and latency-efficient processing of full-text searches over the wireless broadcast data stream. Although a lot of access methods and index structures have been proposed in the past for full-text searches, all of them are targeted for data in disk storage, not wireless broadcast channels. For full-text searches on a wireless broadcast stream, we firstly introduce a naive, inverted list-style indexing method, where inverted lists are placed in front of the data on the wireless channel. In order to reduce the latency overhead, we propose a two-level indexing method which adds another level of index structure to the basic inverted list-style index. In addition, we propose a replication strategy of the index list and index tree to further improve the latency performance. We analyze the performance of the proposed indexing scheme with respect to the latency and energy usage measures, and show the optimality of index replication. The correctness of the analysis is demonstrated through simulation experiments, and the effectiveness of the proposed scheme is shown by implementing a real wireless information delivery system.

A Low-Latency and Memory-Efficient On-chip Network

Abstract: Using multiple SDRAMs in MPSoCs and NoCs to increase memory parallelism is very common nowadays. In-order delivery, resource utilization, and latency are the most critical issues in such architectures. In this paper, we present a novel network interface architecture to cope with these issues efficiently. The proposed network interface exploits a resourceful reordering mechanism to handle the in-order delivery and to increase the resource utilization. A brilliant memory controller is efficiently integrated into this network interface to improve the memory utilization and reduce both memory and network latencies. In addition, to bring compatibility with existing IP cores the proposed network interface utilizes AXI transaction based protocol. Experimental results with synthetic test cases demonstrate that the proposed architecture gives significant improvements in average network latency (12%), average memory access latency (19%), and average memory utilization (22%).

Architectural design for next generation heterogeneous memory systems

Abstract: New enterprise workloads requiring fast, reliable access to increasing amounts of data have pushed today's memory systems to power and capacity limits while creating bottlenecks as they ensure transactions are persistently tracked for reliability. New storage class memory technologies (such as phase change memory) have the potential to offer high capacity within latency and bandwidth ranges acceptable for a computer memory system and persistence which may help ease the system-level burden of balancing performance and reliability. This paper describes architectural options for addressing the challenges of future, heterogeneous memory systems as well as the attributes required of the next generation memory devices.

The impact of latency on online classification learning with concept drift

Abstract: Online classification learners operating under concept drift can be subject to latency in examples arriving at the training base. A discussion of latency and the related notion of example filtering leads to the development of an example life cycle for online learning (OLLC). Latency in a data stream is modelled in a new Example Life-cycle Integrated Simulation Environment (ELISE). In a series of experiments, the online learner algorithm CD3 is evaluated under several drift and latency scenarios. Results show that systems subject to large random latencies can, when drift occurs, suffer substantial deterioration in classification rate with slow recovery.