Showing papers on "Multiplexer published in 1997"

Multiplexed active biologic array

Abstract: An improved biologic electrode array (12) and methods for using the same. Each electrode (30) in the array (12) is coupled to a respective sample-and-hold circuit (26). The electrodes (30) and sample-and-hold circuits (26) are integral and form an array (12) within a single semiconductor chip, such that each sample-and-hold circuit (26) may be loaded (37) with a predefined voltage provided by a single, time-shared digital-to-analog converter (DAC) (22). All of the sample-and-hold circuits (26) may be accessed through a multiplexer which may scan through some or all of the electrode locations (30). Each sample-and-hold circuit (26) may comprise a capacitor (32) and one or more transistor switches (34, 36), the switches (34, 36), when closed providing electrical communication between the capacitor (32) and a source line (37) formed in the matrix (12).

Silicon-on-insulator (SOI) phased-array wavelength multi/demultiplexer with extremely low-polarization sensitivity

Abstract: We demonstrate the first phased-array wavelength multiplexer fabricated in the silicon-on-insulator (SOI) waveguide technology. The four-channel wavelength division multiplexer (WDM) has a channel spacing of 1.9 nm centered at 1550-nm wavelength and a 3-dB channel bandwidth of 0.72 nm. The crosstalk to neighboring channels is less than -22 dB and the on-chip insertion loss is below 6 dB for all channels. The TE-TM shift is less than 0.04 nm which is the smallest attained without compensation techniques in any integrated optic technology.

Athermal silica-based arrayed-waveguide grating multiplexer

Abstract: A temperature dependent channel wavelength shift in a silica-based arrayed-waveguide grating multiplexer is successfully suppressed from 0.95 to 0.05 nm in the 0-85/spl deg/C temperature range, which means that it can be used in practical WDM systems without the need for temperature control.

High-speed protocol for bursty traffic in optical networks

Abstract: An optical backbone network based on WDM (or OTDM) technology may become an economical choice for providing future broadband services. To achieve a balance between the coarse-grain optical circuit switching (via wavelength routing) and fine- grain optical packet/cell switching, optical burst switching is proposed. We study a one-way reservation protocol called just-enough-time (JET), which is suitable for switching bursty traffic in a high speed optical backbone network. The JET protocol has two unique, integrated features, namely, the use of delayed reservation (DR) and buffered burst multiplexers (BBM). By virtue of DR, the JET protocol not only increases the bandwidth utilization, but also facilitates intelligent buffer management in BBMs, and consequently results in a high through-put. Both analysis and simulation results show that the JET protocol can significantly outperform other one-way reservation protocols lacking one or both of these features.

Multi-camera video recording system for vehicles

Abstract: A video recording system for vehicles including a video recorder having an electronic record control input port and a video signal input port; a four-to-one video multiplexer having four multiplexer video signal input ports and one multiplexer video signal output port, the multiplexer video signal output port being in transmitting connection with the video signal input port of the video recorder; an activation switch in electrical connection with the electronic record control input port of the video recorder; and a rear view mirror/camera assembly having four video cameras each with a wide angle fish-eye lens and a camera video signal output port in transmitting connection with one of the four multiplexer video signal input ports, one fish-eye lens being aimed toward the front of the vehicle, one fish-eye lens being aimed at the rear of the vehicle, one fish-eye lens being aimed at the driver seat portion of the passenger compartment, and one fish-eye lens being aimed at the front passenger seat portion of the passenger compartment, the four-to-one video multiplexer switching the camera video signals received at its four multiplexer video signal input ports sequentially to the multiplexer video signal output port in response to an activation signal from the activation switch to the video recorder control input port.

FPGA having logic element carry chains capable of generating wide XOR functions

Abstract: An aspect of the invention provides an FPGA interconnect and logic block structure preferably included in an array of identical tiles. By allowing the complement of a carry multiplexer input signal to be another carry multiplexer input signal, an optional inverter can be formed and a carry chain running from one tile to the next can be used for generating wide XOR functions as well as other combinational functions and arithmetic functions.

A combined analog and digital communications device

Abstract: communications device (200) is presented which is configured to provide selective signal processing at a 'plain old telephone service' (POTS) interface, and ISDN U interface, or an ISDN S/T interface. A first POTS connector (208) allows the communications device to be connected to an analog POTS telephone line. A second ISDN U connector (209) allows the communications device to be connected to an ISDN network at an ISDN U interface point. A third ISDN S/T connector (213) allows the communications device to be connected to an ISDN network at an ISDN S/T interface point. A digital signal processing (DSP) core (202) performs: (i) analog modem functions via analog modem emulation when a POTS telephone line is connected to the POTS connector, or (ii) ISDN digital voice and data processing functions along with ISDN S/T and U interface functions when an ISDN line is connected to the ISDN U connector, or (iii) ISDN digital voice and data processing functions along with ISDN S/T interface functions when an ISDN line is connected to the ISDN S/T connector. Interface logic couples signals between the DSP core and the connectors. A digital data path multiplexer (204) coupled between the DSP core and the interface logic includes 'autosense' logic (2220) which monitors signals received by the connector coupled to the telephone line and determines a data transfer mode based upon the received signals. The digital data path multiplexer provides the data transfer mode information to the DSP core, and the DSP core performs communications operations according to data transfer mode information.

Thermostat with remote temperature sensors and incorporating a measured temperature feature for averaging ambient temperatures at selected sensors

Abstract: A thermostat includes a first temperature sensor integral with the thermostat and at least one and typically three remotely positioned temperature sensors. Switches are provided to select which one or more temperature sensors are employed to provide an averaged measured temperature. Voltages representative of the temperature ambient to each diversely placed sensor are applied to separate inputs to an analog multiplexer which transfers a single voltage to an analog-to-digital converter in accordance with address codes received from a processor. The output of the A-D converter, a digital count representative of the temperature measured by the currently selected sensor, is read by the processor and temporarily saved. Then, the next selected sensor is similarly processed. When all the selected sensors have been processed, the resulting counts are averaged, and the result is conventionally processed, as by passing it through a conversion algorithm, to obtain the averaged temperature which is employed as the measured temperature and compared against a current reference temperature to determine control signals to be sent to one or more environmental modification units such as a heater and/or an air conditioner.

A receiver for a navigation system, in particular a satellite navigation system

Abstract: The invention relates to a navigation system receiver comprising at least two antennas, one of which is a "reference" antenna. A multiplexer multiplexes the signals from the antennas, and a first processor situated downstream from the multiplexer delivers at least one navigation parameter on the basis of the signals from the multiplexer. The receiver includes a second processor having an input receiving in continuous manner signals from the reference antenna to deliver at least one reference signal representative of a position parameter of the reference antenna. Processor means process the signals from the multiplexer while taking account of at least one said reference signal.

32×32 arrayed-waveguide grating multiplexer with uniform loss and cyclic frequency characteristics

Abstract: A 32/spl times/32 arrayed-waveguide grating multiplexer with uniform-loss and cyclic-frequency characteristics has been fabricated on a silica-based planar lightwave circuit. The device consists of an 80-channel arrayed-waveguide multiplexer with 100 GHz spacing and 32 optical combiners which are connected to the 72 output waveguides of the multiplexer. The peak-to-peak loss and channel centre frequency variations are 1.2 dB and 22.3 GHz, respectively, for entire 32/spl times/32 input/output combinations. These values have been substantially improved from conventional arrayed-waveguide multiplexers with peak-to-peak loss and centre frequency variations of 4.7 dB and 75.6 GHz respectively.

Data decoding system and method, transfer device and method, and receiving device and method

Abstract: Data that is an MPEG program stream (PS) read out from a disc is supplied to a PS/TS converter via a variable rate control section. The PS/TS converter converts the PS MPEG data into a transport stream (TS) and transmits it to a presentation device via a 1394 transmission/reception section. Data received by a 1394 transmission/reception section of the presentation device is classified by a DEMUX section. An audio decoder and a video decoder decode the TS MPEG data. D/A converters convert resulting digital data into analog signals and output the analog signals.

Optical add-drop multiplexer

Abstract: An object of the present invention is to provide an optical add-drop multiplexer capable of giving improved characteristics with a simple, inexpensive arrangement which needs not a corresponding number of optical bandpass filters to the wavelength components of a light signal to be carried. The wavelength components λ1 to λn of an input n-wave signal is received by an input optical fiber and transmitted through an optical circulator and an optical fiber to an optical bandpass filter which allows a specific wavelength λ1 to pass but rejects the other wavelengths λ2 to λn. While the rejected wavelengths λ2 to λn are returned back to the optical fiber, the specific wavelength λ1 runs through another optical fiber and another optical circulator and then is dropped from an output optical fiber. Meanwhile, another signal component of the wavelength λ1 is added and introduced from another input optical fiber through the another optical circulator and the another optical fiber to the optical bandpass filter. Upon the added wavelength λ1 having passed the optical bandpass filter and entering the optical fiber, it is mixed with the rejected wavelengths λ2 to λn. A resultant sum signal of the full wavelengths λ1 to λn is passed through the optical circulator and transmitted from an output optical fiber.

Computer system including a refresh controller circuit having a row address strobe multiplexer and associated method

Abstract: A refresh controller circuit in an electronic device, such as a microprocessor unit of a portable computer adapted for docking into a docking station, and a method of operating a computer system to control a refresh operation, are disclosed. The refresh controller circuit includes a refresh clock circuit, a refresh queue counter circuit, and an idle condition detector responsive to the absence of memory read and write requests over a period of time. The refresh controller circuit also includes a latch for storing bits indicative of a self refresh mode enable and a refresh queuing enable. A suspend enable circuit is fed by an output of the idle condition detector and a stop request line, and a refresh request circuit is responsive to outputs of the refresh queue counter, the idle condition detector, and the refresh queuing enable. A refresh row address strobe (RAS) circuit has inputs from the self-refresh circuit and the suspend enable circuit. A RAS multiplexer has inputs for an output of the refresh RAS circuit and for data access RAS, and has an output connected to RAS output terminals of the memory controller for connection to an external dynamic random access memory to effect refresh. The microprocessor unit, which may be integrated onto a single integrated circuit chip with the refresh and memory controller, has a first level write-through cache in combination with a significantly smaller second level write-back cache. The disclosed microprocessor unit also includes configuration registers and circuitry for controlling the access thereto, including circuitry for determining memory address type and bank sizes.

Arithmetic cell for field programmable devices

Abstract: An arithmetic cell to be used in field programmable devices is defined in this invention. This cell will allow efficient implementations of multipliers, multipliers/accumulators and adders (addition, compare, and subtraction) in one compact cell that is a collection of circuits common to field programmable devices. This cell may be used in a flexible manner that allows full multipliers of any dimension (n*m products), adders of any length (n+m sums, compare, differences), accumulators, and registers (to hold complete results or partial products). Key elements in this invention are an application controlled multiplexer, signal routing to provide a shift function for multiplication, and a minimum collection of configuration bits and circuit elements to perform the basic arithmetic functions.

Diffraction grating with reduced polarization sensitivity

Abstract: A multiplexer/demultiplexer (10) for routing different wavelength signals between a common pathway (12) for conveying a plurality of the signals, and individual pathways (14a-14b) for separately conveying the signals, includes a reflective diffraction grating (16) with reduced polarization sensitivity for dispersing the signals. The grating (16) includes facets (20) that are oriented for reducing efficiency variations within a transmission bandwidth and that are shaped for reducing differences between the diffraction efficiencies in two orthogonal directions of polarization.

InP-based 64-channel arrayed waveguide grating with 50 GHz channel spacing and up to -20 dB crosstalk

Abstract: The largest-scale arrayed-waveguide-grating multiplexer ever has been fabricated on an InP substrate. The device has 64 input/ output ports with 0.4 nm (50 GHz) channel spacing and a chip size as small as 3.6/spl times/7.0 mm. The crosstalk is <-20 dB for neighbouring and all other channels.

Reconfigurable wavelength division multiplex add/drop device using micromirrors

Abstract: A WDM add/drop device for use in an optic communications system for adding and dropping optical wavelengths from a multiple-wavelength optical system. The device includes a set of lenses, a planar grating wavelength multiplexer and a micromirror array switchable for individual wavelengths of the multiple-wavelength signal between a transmit mode and a reflect mode. The grating angularly demultiplexes a multiple-wavelength optical signal in a first direction and the individual wavelengths are processed by the micromirror array and directed to the grating in a second direction. The micromirror array will either reflect select wavelengths to a first port or transmit select wavelengths to a second port. In a preferred embodiment, ports on a first multiport circulator input the multiple-wavelength optical signal to the WDM add/drop device and output the multiple-wavelength optical signal from the WDM add/drop device. A second multiport circulator provides to-be-added wavelengths to the WDM add/drop device and removes to-be-dropped wavelengths from the WDM add/drop device.

Design of phased-array wavelength division multiplexers using multimode interference couplers.

Abstract: Novel designs for phased-array wavelength-division multiplexers based on self-imaging properties of multimode interference (MMI) couplers are presented. These devices, which operate on N equally spaced wavelength channels, consist of two MMI couplers connected by an array of N monomode waveguides. The MMI couplers function as power splitters/combiners, and the waveguide array is the dispersive element. The excellent characteristics of MMI couplers offer the possibility of designing small-size devices with low loss and with high uniformity among different channels. A general theoretical formulation for an N-channel multiplexer is presented, and a simple procedure for finding an optimum set of lengths for the array guides is given. We show that these multiplexers can function as N x N wavelength-selective interconnecting components. The simulated performance of three variations of a five-channel device, designed in a rib waveguide system, is given. It is demonstrated that sidelobes in the multiplexer spectral response can be suppressed by weighting the power samples in the array waveguides through appropriate design of a nonuniform MMI power splitter.

Elimination of polarization sensitivity in silica-based wavelength division multiplexer using a polyimide half waveplate

Abstract: This paper proposes a low-loss technique for eliminating polarization sensitivity in a silica-based planar lightwave circuit (PLC) which uses a polarization mode converter formed at the center of the circuit. This converter consists of a waveguide gap housing a polyimide half waveplate. The excess loss of the converter was drastically reduced to 0.26 dB with a /spl Delta/=0.75% waveguide by employing an 18 /spl mu/m-wide waveguide gap and a 14.5 /spl mu/m-thick polyimide half waveplate. A polarization mode conversion crosstalk of -37 dB was achieved at 1.55 /spl mu/m. Using this converter, we successfully eliminated the polarization sensitivity in some silica-based PLC-type wavelength division multiplexers. The converter is also insensitive to temperature and offers long term stability.

Fast bist architecture with flexible standard interface

Abstract: A built-in self test architecture for testing one or more integrated circuits. Each circuit is provided with an interface compatible with IEEE standard 1149.1 and one or more scan registers containing scan cells for supplying input test data to, and receiving output test data from, the internal circuitry of the integrated circuits, a pseudo-random pattern generator for supplying patterns of test data to the boundary scan register, and a pattern compressor for compressing the output test data into a signature. The architecture also includes a single clock multiplexer, located external to the integrated circuits, for selectively supplying a system clock or a test clock to the testing components of each integrated circuit.

Optical communications system with wavelength division multiplexing

Abstract: A wavelength division multiplexer (WDM) in an optical fiber transmission system launches analog signals, for instance a multi-channel television signal. The WDM enhances signal quality by transmitting along a single fiber two different optical wavelength signals, each carrying identical RF information. This results in a 3 dB improvement in carrier to noise ratio. The WDM combines two or more wavelengths centered around for instance 1550 nm or 1310 nm. A typical difference between the two wavelengths is 3 nm. In other embodiments, more than two wavelengths are used. The receiver is for instance a single photosensitive element. The phase of the two RF signals is adjusted in the optical or RF domain to be the same upon arrival at the receiver. In other embodiments, the receiver includes two photosensitive elements, each receiving from a receiver end WDM a single wavelength. In this case, the phase adjustment may be applied at the receiver in the optical or RF domain.

Apparatus and method for multi-service transport multiplexing

Abstract: An elementary two-stream transport multiplexer provides for the addition of services contained in a transport stream to a pre-existing transport stream. The elementary multiplexer includes a pair of transport demultiplexers, a processor and a transport remultiplexer. The demultiplexers demultiplex a pair of input transport streams to their constituent service components and service control information tables. The service control information tables are routed to the processor which combines and reconfigures the information within the tables to provide a single set of output service control information tables. The demultiplexers filter the service components based on the output service control tables. The transport remultiplexer multiplexes the output tables with the filtered streams to provide an output transport stream.

Read/write channel write precompensation system and method using one or more delay clocks

Abstract: An improved write precompensation circuit for a read/write channel circuit and system is provided. Multiple data input signals are provided, each being clocked by a different clock. The data input signals are then multiplexed. Two, three or more data clock delays may be utilized to provide two, three or more data delays to achieve the write precompensation. Only one edge of a signal need pass through a multiplexer before the multiplexer may change state. The amount of delay may be user programmable.

Floating-body effects in partially depleted SOI CMOS circuits

Abstract: This paper presents a detailed study on the impact of a floating body in partially depleted (PD) silicon-on-insulator (SOI) MOSFET's on various CMOS circuits. Digital very large scale integration (VLSI) CMOS circuit families including static and dynamic CMOS logic, static cascade voltage switch logic (static CVSL), and dynamic cascade voltage switch logic (dynamic CVSL) are investigated with particular emphasis on circuit topologies where the parasitic bipolar effect resulting from the floating body affects the circuit operation and stability. Commonly used circuit building blocks for fast arithmetic operations in processor data-flow, such as static and dynamic carry lookahead circuits and Manchester carry chains, are examined. Pass-transistor-based designs including latch, multiplexer, and pseudo two-phase dynamic logic are then discussed. It is shown that under certain circuit topologies and switching patterns, the parasitic bipolar effect causes extra power consumption and degrades the noise margin and stability of the circuits. In certain dynamic circuits, the parasitic bipolar effect is shown to cause logic state error if not properly accounted for.

Polymeric arrayed-waveguide grating multiplexer with wide tuning range

Abstract: A 0.8 nm spacing polymeric arrayed-waveguide grating (AWG) multiplexer operating around 1550 nm is realised using a silicone resin waveguide. The AWG multiplexer has an insertion loss in the range 9-13 dB, a crosstalk of <-20 dB, and a polarisation-dependent wavelength shift of 0.35 nm. The transmission peak wavelength is tunable over 10 nm with a temperature change of 55/spl deg/C.

Configurable logic block with AND gate for efficient multiplication in FPGAS

Abstract: An improved CLB architecture, wherein the use of dedicated AND gates to generate a carry chain input signal facilitates low latency multiplication and makes efficient use of four-input function generators. In one embodiment of the invention, when multiplication using a binary addition tree algorithm is used, AND gates to implement single-bit multiplication are provided within the available function generators and duplicated in a dedicated AND gate accessible outside the corresponding function generator as a carry-chain input signal. In another embodiment, carry chain multiplexers can be selectively configured as AND or OR gates to facilitate certain arithmetic or comparison functions for the outputs of a plurality of function generators.

Input signal interface with independently controllable pull-up and pull-down circuitry

Abstract: An input interface circuit for a logic device having a configuration of pull-up and pull-down devices for defining the logic level based on an undriven input signal where the pull-up and pull-down devices are independently and separately programmable to follow the input signal (e.g., a keeper circuit), or follow the inverse of the input signal, or programmed permanently on, or programmed permanently off. The interface circuit can be used to provide a known and programmable output signal for an IC input (or internal line) that does not have a known driving source. By allowing this degree of flexibility, the input interface circuit of the present invention, under programmed control, generates an output signal with positive or negative feedback based on the input signal; or the input interface circuit provides a constant high or constant low signal output, or can oscillate or provide a high impedance response as output. In cases when the input pin (or internal line) is not being driven by a bus or source driver, the input interface provides a number of flexible configurations for supplying predetermined outputs. Within a programmable logic device, a separate input interface circuit is provided with each external pad (or internal line) that provides signals within the integrated circuit originating from associated input pins. The input interface contains two multiplexers which drive the pull-up and pull-down devices, each multiplexer being coupled to receive inputs from programmable memory cells and having a common control line.

Programmable logic device with highly routable interconnect

Abstract: A programmable logic device architecture with a highly routable programmable interconnect structure. The arrangement of the logic array blocks (LABs), programmable interconnect structure, and other logical elements forms a Clos network. After specific constraints have been met, the architecture is guaranteed to route. The architecture is provably routable when there is no fan-out in the middle stage. A LAB ( 200 ) comprises an input multiplexer region ( 504 ), logic elements ( 300 ), input-output pins ( 516 ), and output multiplexer region ( 508 ).

Optical add/drop multiplexer based on UV-written Bragg grating in a fused 100% coupler

Abstract: The authors report the first realisation of a simple and stable optical add/drop multiplexer based on a UV-written Bragg grating in the coupling region of a fused 100% coupler. Add/drop functions are demonstrated with a low insertion loss (<1 dB).

Configurable logic element with fast feedback paths

Abstract: The invention provides an FPGA interconnect structure preferably included in an array of identical tiles. Each tile comprises a logic block that includes a Configurable Logic Element (CLE) and an output multiplexer. Fast feedback paths are provided within the logic block to connect the CLE outputs to the CLE inputs, either directly or through an input multiplexer. The fast feedback paths bypass the output multiplexer and therefore provide faster feedback than can be obtained in most conventional FPGA logic blocks. In one embodiment, the fast feedback paths provide the ability for all function generators in one CLE to drive each other through fast feedback paths, regardless of how logic is mapped into the function generators of the CLE.