Showing papers on "Pass transistor logic published in 1993"

Reversible electronic logic using switches

Abstract: Two methods of using switches to implement reversible computations are discussed. The first method has an energy dissipation which is proportional to the square of the error in the voltage, while the second method has an energy dissipation which can in principle be reduced indefinitely by slowing the speed of computation. The first method is basically an extension to 'pass logic' which has been previously used with both nMOS (hot clock nMOS) and CMOS transmission gates to achieve low energy dissipation. The second method is a novel thermodynamically reversible logic system based on CCD-like operations which switches charge packets in a reversible fashion to achieve low energy dissipation.

Technology Mapping for Low Power

Abstract: The last couple of years have seen the addition of a new dimension in the evaluation of circuit quality - its power requirements. Low power circuits are emerging as an important application domain, and synthesis for low power is demanding attention. The research presented in this paper addresses one aspect of low power synthesis. It focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with power as the optimization metric. Several issues in modeling and measuring circuit power, as well as algorithms for technology mapping for low power are presented here. Empirically, it is observed that a significant variation in the power consumption is possible just by varying the choice of gates. Technology mapping for low power provides circuits with up to 24% lower power requirements than those obtained by technology mapping for area.

A New Resonant Tunneling Logic Gate Employing Monostable-Bistable Transition

Abstract: This letter describes a new resonant tunneling logic gate. The concept of the proposed gate has two features: 1) to employ the monostable-to-bistable transition of a circuit consisting of two N-type negative differential resistance (NDR) devices connected serially, and 2) to drive the logic gate by oscillating the bias voltage to produce the transition. This mode of operation has a significant advantage in that a large number of fanouts is possible without sacrificing the high-speed operation. Serially connected resonant tunneling field effect transistors having p+-junction gates were fabricated to test the above operation principle. The inverter operation of the proposed logic gate has been successfully achieved at room temperature.

An efficient logic emulation system

Abstract: The Realizer, is a logic emulation system that automatically configures a network of field-programmable gate arrays (FPGAs) to implement large digital logic designs, is presented. Logic and interconnect are separated to achieve optimum FPGA utilization. Its interconnection architecture, called the partial crossbar, greatly reduces system-level placement and routing complexity, achieves bounded interconnect delay, scales linearly with pin count, and allows hierarchical expansion to systems with hundreds of thousands of FPGA devices in a fast and uniform way. An actual multiboard system has been built, using 42 Xilinx XC3090 FPGAs for logic. Several designs, including a 32-b CPU datapath, have been automatically realized and operated at speed. They demonstrate very good FPGA utilization. The Realizer has applications in logic verification and prototyping, simulation, architecture development, and special-purpose execution. >

Implementation of redundancy on a programmable logic device

Abstract: An improved architecture and method of operation for providing redundancy in programmable logic devices. Spare columns or rows of logic blocks 115 and switch boxes 140 are employed to replace columns or rows of logic blocks containing one or more defective logic blocks. Associated logic enable the device to bypass a column or row of logic blocks 115 containing one or more defective logic blocks 115 and to switch in a spare column or row of defect-free logic blocks 115 as replacement.

Voltage boosting circuit of the charge pump type with bootstrap oscillator

Abstract: The invention relates to charge-pump circuits used for the generation, in an integrated circuit, of an internal supply voltage Vpp which is considerably greater than the external supply voltage Vcc. In a charge pump configuration with capacitors and transistors, certain transistors must be driven by bootstrapped logic signals, i.e., having a logic level which is greater than Vcc in order to overcome the threshold voltage of the transistors. According to the invention, there is an oscillator followed by a phase splitter stage which is in turn followed by a bootstrap amplifier stage. The oscillator is a ring oscillator having a number of logic gates which is as small as possible, preferably only three. A satisfactory frequency stability of the charge pump is thus obtained and therefore its design is made easier and its adaptability to various electronic circuits is improved.

Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal ICs

Abstract: CMOS folded source-coupled logic (FSCL) uses a smaller logic voltage swing ( Delta V/sub L/ approximately=0.2 V/sub dd/) than conventional static logic and achieves a smaller power-delay product at high operating frequencies. By using current-steering techniques in fully-differential FSCL circuits to maintain a constant power supply current, digital switching noise is reduced by 30-300 times compared to conventional CMOS static logic. Measured results are presented for FSCL gates fabricated in a 2- mu m CMOS process, and simulated results with a standard 1- mu m process are used to compare the power, delay, and switching noise characteristics of FSCL and static logic with 5.0-, 3.3-, and 2.0-V power supplies. >

CMOS low power mixed voltage bidirectional I/O buffer

Abstract: This invention describes the design and implementation of a low power CMOS bidirectional I/O buffer that translates low voltage core logic level signals into the highest logic level signals to drive the final output stage which outputs a selectable logic level signal. The invention further translates input signals of a variety of logic levels into low voltage core logic level signals. In either case, AC and DC power consumption is minimized in a mixed power supply environment that requires voltage translation to represent the proper binary logic levels.

System powered with inter-coupled charge pumps

Abstract: A multi-phase charge pump continuously pumps to establish a DC voltage outside the range of supply and reference voltages The multi-phase charge pump in one embodiment includes four stages operating in a ring with a four-phase clock Each stage includes a three-mode charge pump that generates and provides reset and control signals to other stages Each stage includes a pass transistor having a gate driven in excess of the DC voltage for efficient transfer of charge The gate drive signal from a first stage is coupled to a next stage in the ring where it is used to generate the next gate drive signal Each gate drive signal corresponds to one waveform having a phase skewed in time so that each stage in the ring is operating in a different mode In a method of use, a first stepped voltage is developed on a first capacitor and selectively coupled to a second capacitor to develop a second stepped voltage of greater absolute value The second stepped voltage gates charge transfer from a first stage and enables the selective coupling in a next stage in a sequence of pump stages The pump stages include protection circuits protecting high-voltage nodes during burn-in testing The charge pump includes a burn-in detector circuit for detecting burn-in conditions and for turning on the protection circuits and a pump regulator for regulating the output of the charge pump

Weighted sum threshold logic operation of MOBILE (monostable-bistable transition logic element) using resonant-tunneling transistors

Abstract: The functional operation of the MOBILE (monostable-bistable transition logic element) has been studied using multiple-input logic gates. The MOBILE uses two resonant-tunneling transistors (RTTs) connected in series and driven by an oscillating bias voltage to produce a mono-to-bistable transition of the circuit. A MOBILE having three input gates with a 1:2:4 width ratio can distinguish all 8 (2/sup 3/) input patterns corresponding to each weighted sum, depending on the threshold value selected by the control gate. The results confirm the realization of the weighted sum threshold logic operation of input signals. >

CMOS multiple-valued logic design. I. Circuit implementation

Abstract: A CMOS circuit implementation of a functionally complete multiple-valued logic (MVL) set of operators is proposed. The set consists of literal, cycle, complement of literal, complement of cycle, min, and tsum operators. In all of the circuits, multiple-valued logic levels are represented in terms of current values. Binary voltage signals are generated inside the circuits using a threshold circuit element. These binary voltage signals are used to generate control signals for switches to realize appropriate current levels for the desired multiple-valued logic levels. Transient analysis simulations (using HSPICE) to verify the functionality of the designed circuits and the effect of variation in process parameters are also reported. >

Design and application of pipelined dynamic CMOS ternary logic and simple ternary differential logic

Abstract: Dynamic CMOS ternary logic circuits that can be used to form a pipelined system with nonoverlapped two-phase clocks are proposed and investigated. The proposed dynamic ternary gates do not dissipate DC power and have full voltage swings. A circuit structure called the simple ternary differential logic (STDL) is also proposed and analyzed, and an optimal procedure is developed. An experimental chip has been fabricated in a 1.2- mu m CMOS process and tested. A binary pipelined multiplier has been designed, using the proposed dynamic ternary logic circuits in the interior of the multiplier for coding of radix-2 redundant positive-digit number. The structure has the advantages of higher operating frequency, less latency, and lower device count as compared with the conventional binary parallel pipelined multiplier. The advantages of the circuits over other dynamic ternary logic circuits are shown. >

Logic design based on negative differential resistance characteristics of quantum electronic devices

Abstract: New quantum electronic devices such as resonant tunnelling diodes and transistors have negative differential resistance characteristics that can be exploited to design novel high-speed circuits. The high intrinsic switching speed of these devices, combined with the novel circuit structures used to implement standard logic functions, leads to ultrafast computing circuits. The new circuit structures presented here provide extremely compact implementations of functions such as carry generation and addition. The most significant impact of these circuits on the field of logic design is the introduction of a totally new set of relative costs of various basic gates; reevaluation of the logic in the light of these new cost functions leads to ultrafast and compact designs.

Programmable logic devices with spare circuits for replacement of defects

Abstract: A programmable, integrated circuit, logic array device has several regular logic groups and at least one spare logic group. If any of the regular logic groups is defective, the spare logic group is used to make up for the defective logic group. To accomplish this, programming and data input signals that would normally go to the defective logic group are redirected to another logic group. The data output signals of the other group are substituted for the data output signals of the logic group that would normally have received the programming and data input signals that were redirected to the other logic group.

Method and apparatus for controlling a mixed voltage interface in a multivoltage system

Abstract: The design and implementation of a low power CMOS bi-directional I/O buffer that translates low voltage core logic level signals into the highest logic level signals to drive the final output stage which outputs a selectable logic level signal. The buffer further translates input signals of a variety of logic levels into low voltage core logic level signals. In either case, AC and DC power consumption is minimized in a mixed power supply environment that requires voltage translation to represent the proper binary logic levels. An multivoltage I/O buffer having multiple input-receiving NOR gates is also described. The NOR gates of the multivoltage I/O buffer having triggering levels optimized for differing core voltage levels. Also described is a host adapted system for interfacing between and removable peripheral card and a host computer. The host adaptor includes an integrated circuit employing the multivoltage bi-directional I/O buffer.

Programmable logic array having programmable output driver drive capacity

Abstract: A programmable logic array includes configurable logic cells disposed in lines and columns. Each of the logic cells has signal inputs, control inputs, at least one signal output, and an output driver circuit connected upstream of the at least one signal output. The output driver circuit has a terminal for a first and a second supply potential and is connected to at least one of the control inputs. The output driver circuit is controllable for setting its driver capacity to a level other than zero, corresponding to a signal value, by a digital signal applied to the at least one control input. Conductor tracks and switching elements for interconnecting the conductor tracks connect the at least one signal output of each of the logic cells to at least one of the signal inputs of at least another one of the logic cells.

Very low voltage inter-chip CMOS logic signaling for large numbers of high-speed output lines each associated with large capacitive loads

Abstract: A CMOS integrated circuit (IC) device embodiment of the present invention comprises an internal logic circuit operating with traditional 3.3 volt or five volt internal logic levels, an output buffer to convert the internal logic levels to external logic levels of 0.3 volts and an input buffer to convert the 0.3 volt external logic levels to the internal logic levels. In a CMOS IC device having numerous external output loads including relatively high capacitive values that are driven at very high clock rates, the restricted voltage swings of the 0.3 volt external logic levels permit unusually large numbers of devices to be driven without exceeding a predetermined power dissipation limit of the CMOS IC device. The low external logic levels further permit electrostatic discharge (ESD) protection to be included on all signal inputs and outputs of the CMOS IC device. The ESD protection comprises a pair of opposite polarity silicon PN junction diodes in parallel and connected between each signal line and a ground reference.

Multiple-valued logic in FPGAs

Abstract: This paper considers the applicability of multiple-valued logic (MVL) circuits in implementation of field-programmable gate arrays (FPGAs). It proposes an FPGA logic block architecture that features MVL current-mode CMOS circuitry. The logic block combines the lookup-table and multiplexer approaches found in commercial FPGAs, and provides additional versatility through its current-mode operation. >

Recovered energy logic-A highly efficient alternative to today's logic circuits

Abstract: Recovered energy logic (REL) is a system approach to the reduction of dissipation in logic circuits. It embodies a new logic circuit topology and a power supply/clocking circuit. The logic topology of REL is described, and simulation results from a MOS implementation are given. The detailed design of a power supply that could be used to drive a REL circuit at up to 100 MHz is described. >

Real-time reconfigurable logic circuits using neuron MOS transistors

Abstract: A highly-flexible real-time-reconfigurable logic circuit implemented using a regular CMOS process is presented. The circuit, called soft-hardware logic (SHL), can alter its logic function (e.g. AND, OR, NAND, NOR, Exclusive OR, Exclusive NOR) in real time according to external control signals with no hardware modification. The circuit is one application of the neuron MOSFET (neuMOS or vMOS), a multiple-input functional MOS transistor simulating the function of biological neurons by a single device. The concept has been verified by experiments using test circuits fabricated by a standard double-polysilicon CMOS process. Details on the operational principle of the SHL circuit as well as design techniques are presented. One extension of this vMOS concept is a dynamic data-matching circuit in which rules for data matching are time-variable. Circuit operation has been verified by experiments. >

Analog logic techniques steer around the noise

Abstract: CMOS folded source-coupled logic (FSCL) and current-steering logic (CSL), developed to complement conventional CMOS static logic in high-precision mixed-signal applications, are examined. The key feature of FSCL and CSL is the reduction in power-supply noise-current spikes by two orders of magnitude or more compared to conventional CMOS logic. Hence, FSCL and CSL are attractive for the high-speed logic sections of CMOS mixed-mode integrated circuits, while conventional logic is appropriate for the low-speed digital subsections. >

Self-timed interconnect speed-up circuit

Abstract: A circuit style, which may be employed in fast, area-efficient, flexible programmable interconnect architectures, or in logic circuits, is disclosed. In one embodiment, a plurality of internally delayed logic circuits, each having a single network node, is connected to the intermediate nodes of a programmable interconnect architecture. Each speed-up circuit monitors the logic level on the network node. When a circuit detects a substantial change in logic level, it temporarily enforces that change by connecting its network node to either the high or the low logic level. Thus, on each node, a low-impedance enhancement of the signal driving the node temporarily appears. This causes the potential on neighboring nodes, connected through conducting programmable switches, to change towards the new level, and their speed-up circuits in turn temporarily enforce the new level. Thus, a forced high-to-low or low-to-high level change on a node quickly propagates to its connected nodes.

Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering

Abstract: A method which uses transistor reordering for the performance enhancement of CMOS circuits is presented. The proposed technique achieves significant reduction in propagation delays with little effect on layout area. The technique can be coupled with transistor sizing to achieve unbounded improvement in circuit delay, and it can be used to decrease dynamic power dissipation. In particular, excellent results have been achieved when the method is applied to data path circuits.

Dynamic control of configurable logic

Abstract: A method and device for performing logic functions. A logic array (1) is controlled by a plurality of DRAM cells (101). The DRAM cells are, in preferred embodiments, loaded in a serial fashion with a shift register (1205). Refresh according to one aspect of the invention utilizes a shift register (1201) with a circulating "0." A charge pump circuit, voltage boost circuit, and a variety of memory cell/logic array configurations are also disclosed.

A dual granularity and globally interconnected architecture for a programmable logic device

Abstract: A novel architecture called FLEX (flexible logic element matrix) has been designed which supports high logic densities up to 24,000 gates, maximizing overall system performance in a user design. This has been accomplished through a dual granularity approach and a global interconnect strategy. The dual granularity and global interconnect approach has succeeded in supporting both short nets and long nets for maximum performance.

Self-timed clocking system and method for self-timed dynamic logic circuits

Abstract: A clocking system and method are provided for logic blocks having cascaded self-timed dynamic logic gates. The dynamic logic gates are precharged in parallel and collectively perform self-timed logic evaluation on vector inputs to derive a vector output. An evaluation done detector monitors the output of the logic block and determines when the vector output is valid. An edge detector detects the rising and falling edges of an arbitrary periodic timing signal. Finally, a logic block clock generator is set by the edge detector and reset by the evaluation done detector so as to provide precharging signals to the logic block, thereby defining respective precharge periods, and to provide evaluation periods for the self-timed logic evaluations in the logic block. In a specific implementation, the speed of logic evaluations is twice the speed of the system clock.

Tracking run/standby power supplies

Abstract: A power supply for a television apparatus, comprises a first source of unregulated DO run voltage operable only in a run mode of operation and a second source of unregulated DO voltage operable in a standby mode and in the run mode of operation. A first regulator responsive to the first source unregulated DO run voltage produces a first regulated voltage. A second regulator responsive to the second source of unregulated DO voltage produces a second regulated voltage. First and second integrated circuits are energized respectively by the first and second regulated voltages. At least one of the integrated circuits has a signal output coupled to a signal input of the other of the integrated circuits. A controller is operable in the run mode and responsive to variations of one of the regulated voltages for adjusting the other of the regulated voltages to follow the variations. Each of the regulators may comprise a series pass transistor and a control transistor coupled to a base of the series pass transistor. Each of the control transistors provides a control current. The controller can be responsive to both control currents for adjusting the regulated voltages to track one another. The control circuit may sum the control currents.

Adaptive clock duty cycle controller

Abstract: An adaptive clock duty cycle controller which generates a dc error signal that is supplied to a logic device, such as a logic inverter or a logic buffer, which outputs a specified duty cycle clock signal. The output of the logic device is supplied to a positive peak detector, a negative peak detector and an average signal level detector. The output of the positive peak detector and the negative peak detector are supplied to a mid-peak generating circuit which generates a signal for setting and maintaining the desired duty cycle. The signal output by the average signal level detector represents the average value of the output of the logic device. The signal output by the mid-peak generating circuit is compared with the signal output by the average signal level detector by an operational amplifier. The output of the operational amplifier represents the error signal which is supplied back to the input of the logic device to control the output of the logic device to the desired duty cycle.

Programmable logic circuit

Abstract: A programmable logic circuit is provided with a plurality of logic cells including specific logic cells, at least two sub blocks, included in the specific logic cell, respectively having two or more inputs and one or more outputs and having only a predetermined combinational logic function by itself, and a switching circuit, included in the specific logic cell, and capable of independently connecting a path between the input and output of each sub block. An arbitrary combinational logic function and an arbitrary sequential logic function are realized by programming ON/OFF states of the switching circuit.

Differential pass-transistor logic

Abstract: Differential pass-transistor logic (DPTL), which offers the noise immunity needed to use the unique switching properties of FETs in realizing switching network efficiencies, is discussed. CMOS DPTL offers significant power-delay product advantages over conventional CMOS logic for both 5-V and 3-V power supplies. These features are achieved by DPTL's fewer and smaller parasitic capacitances, which are the result of significantly lower device counts combined with emphasized usage of minimum-size, n-channel pass-transistors. Substantial benefits are also obtained by using DPTL with depletion and enhancement/depletion GaAs MESFET technologies. Experiments show that GaAs DPTL offers substantial power-delay-product reductions over conventional GaAs realizations. Compared to CMOS DPTL, GaAs DPTL consumes less power at very high frequencies, a consequence of the electronic properties of GaAs and the smaller signal swings used in emitter/drain (E/D) DPTL. >