Showing papers on "Pass transistor logic published in 2021"

Recent Advances on Linear Low-Dropout Regulators

Abstract: This brief revises the recent design trends of linear low-dropout regulators. The design issues and advantages of analog LDOs (ALDO) are discussed. High-performance operation and high rejection to supply noise when delivering large current values is a major advantage of the ALDO, but transient response when transitioning from standby operation to full load is a major issue; the main limitation is the slow charging/discharging of the large gate’s capacitor of the pass transistor. This issue is more critical when designing full-on chip ALDOs, where large load capacitors are not available. Digital LDOs (DLDO) employ digital controllers that drive the segmented pass transistor, in most of the cases operate in triode region. The digital nature of the DLDO scales with the technology, but its rejection to supply noise is limited. Mixed-mode LDOs take advantage of the properties of both ALDO and DLDOs. Transient is managed by the agile DLDO and steady state operation is mainly handled by the clock glitch free ALDO. In this brief, all three architectures are revisited.

Synaptic Weight Evolution and Charge Trapping Mechanisms in a Synaptic Pass-Transistor Operation With a Direct Potential Output

Abstract: We present an intensive study on the weight modulation and charge trapping mechanisms of the synaptic transistor based on a pass-transistor concept for the direct voltage output. In this article, the pass-transistor concept for a metal–oxide–semiconductor field-effect transistor is employed to a synaptic transistor with a charge trapping layer, which is named a synaptic pass transistor (SPT). Based on this SPT concept, the voltage signal would be provided at the output terminal directly without requiring a complicated circuitry, whereas the conventional synaptic transistor with the current output needs a conversion circuit. For the SPT, the definition of the synaptic weight as a transfer efficiency and operation principles of the SPT with charge-trapping mechanisms is analyzed theoretically. The respective semiconductor device simulation results, such as synaptic output and weight modulations as a function of time for a synaptic depression and facilitation, are presented with detailed analysis. Also, it is shown that an SPT array configuration can perform a synaptic scaling by itself, i.e., a self-normalization of the weight, which is confirmed with the simulation results of learning a simple classification example. Moreover, to verify the potential usage of the SPT array as an analog artificial intelligence accelerator, a classification task for a standard data set, e.g., Modified National Institute of Standards and Technology database (MNIST), is also tested by monitoring the accuracy. Finally, it is found that SPTs proposed here can exhibit low power consumption at a device level as well as sufficient accuracy at the array level while more closely mimicking the biological synapse.

Hybrid Pass Transistor Logic With Ambipolar Transistors

Abstract: The pass transistor logic (PTL) family enables compact circuits to reduce area and power consumption, but inter-stage inverters are required for signal integrity and complementary signals. Similarly, dual-gate ambipolar field-effect transistors are exceptionally logically expressive and provide a single-transistor XNOR operation, but numerous inverters are required to provide complementary signals. In both cases, these inverters and complementary signals significantly degrade overall system efficiency. Ambipolar field-effect transistors are a natural match for PTL, and we therefore propose a new hybrid ambipolar-PTL logic family that exploits the compact logic of PTL and the ambipolar capabilities of ambipolar field-effect transistors. This logic family is a hybrid between PTL and static CMOS-like logic that is made efficient by the use of ambipolar transistors. Novel hybrid ambipolar-PTL circuits were designed and simulated in SPICE, demonstrating strong signal integrity along with the efficiency advantages of using the required inverters to simultaneously satisfy the requirements of PTL and ambipolar circuits. In comparison to the ambipolar field-effect transistors in the conventional static CMOS logic structure, the proposed ambipolar-PTL family can reduce propagation delay by 33%, energy consumption by 88%, energy-delay product by a factor of 10, and area-energy-delay product by a factor greater than 20.

Design an Area Efficient Kogge Stone Adder using Pass Transistor Logic

Abstract: In recent technologies of Electronics applications, Adder is an important source of any devices such as DSP, VLSI applications For which, many electronics application devices used the high speed adders namely Parallel Prefix Adder (PPA) Generally, PP Adders have less delay due to its less waiting time of carry for next addition But the area consumption is more, in which the performance of the adders will decrease for higher order bits’ addition This paper is to design an area efficient Kogge Stone PPA which performs the parallel arithmetic operations in CMOS applications and analysed the design based on the parameters like area and power individually The proposed area efficient KSA design used the Pass Transistor Logic (PTL) and analysed the performance of particular design The Performance results of PTL with PP-KSA design used the reduce number of MOS devices which yields less area consumption compared to basic design of 4-bit PP-KSA Entire analysis results of these designs can be done in Microwind CMOS tool

Performance Analysis of CMOS, PTL and GDI Based Braun Multiplier for Signal Processing Applications

Abstract: Power, speed and area are key design constraints in signal processing for computing applications as well as for handy electronic gadgets. Multiplier plays a significant role in energy efficient signal processing applications in digital systems. Product of large bit numbers occurs efficiently through binary multiplication. A low power and high speed Gate Diffusion Input (GDI) based Braun multiplier with improved row and column bypassing scheme is presented in this paper. From the simulated results, it is observed that, the GDI based Braun multiplier achieves energy savings more than 4% and up to 99% with CMOS and other methods and in the same way EDP savings more than 15% and up to 30% with CMOS and other methods by means of column and row bypassing techniques. From the layout, it is also analyzed that, GDI Braun multiplier is area efficient over CMOS and its other counter parts at the penalty of 9% more area in comparison with pass transistor logic (PTL) based column and row bypassing techniques.

Design of Two Stage Operational Amplifier and Implementation of Flash ADC

Abstract: In this paper, Flash Analog to digital converter is implemented whose resolution is 3-bits. The designed Flash ADC consists of a resistive ladder network, comparators, the thermometer to a binary encoder and the entire design is carried out using LTspice tools employing 180nm technology. The reference voltage applied to the resistive ladder network is 1.8V. A two-stage operational amplifier is used as a comparator in the flash ADC. Binary code is obtained from the thermometer code by utilizing a priority encoder. The major problem that usually appears in flash ADC is as the number of resolution bits increases, the Area, as well as the power consumption of the circuit, also increases. In this paper, we principally concentrated to lessen the power consumption of the ADC by optimizing encoder circuitry. With the purpose of reducing power consumption, Encoder is implemented using 2:1 mux based on various logics such as switch logic, pass transistor logic as well as CMOS logic. In addition to this, the Wallace tree encoder was also implemented. Performance parameters of Flash ADC such as conversion time as well as average power are calculated and compared. It is verified average power obtained using Wallace tree encoder is 910pW and it is less compared to encoder implemented with other designs.

A Novel High-Performance Hybrid Full Adder for VLSI Circuits

Abstract: This article presents a high-performance hybrid full adder (HPHFA) designed with static CMOS logic and pass transistor logic to achieve better power delay product (PDP). The circuit was implemented using cadence virtuoso tool on gpdk 90 nm and 45 nm CMOS process technologies. Further, the structure has been extended to 32 bits to test the performance of HPHFA in higher-order circuitry. The proposed design was compared with popular conventional adders based on power consumption, delay and PDP. The proposed adder cell achieves 5.08–70.50% and 6.31–48.03% improvement in speed and power consumption, respectively, in 45 nm when compared to other conventional full adders (FAs). Also, the proposed design exhibits robustness against process variation and noise immunity with better driving capability.

A Capacitor-less LDO with High PSR over a wide frequency range

Abstract: This paper presents a capacitor-less low dropout (LDO) voltage PMOS regulator with high power supply rejection (PSR). The proposed LDO combines into a single core two differential stages: a primary one - as error amplifier for the negative feedback loop - and a secondary one, used to create a feedforward cancellation path from the supply to the gate of the pass transistor. With this arrangement the LDO can provide a PSR of -43dB at 1MHz for the maximum load current of 50mA. This performance is achieved with only 20µA quiescent current and a load capacitor of 100pF. The LDO is designed in a 0.18µm standard CMOS process.

Variability Analysis of SBOX With CMOS 45 nm Technology

Abstract: The consistent scaling of metal-oxide-semiconductor field-effect transistor devices lead to parameter variations which become a significant design challenge for the researchers and designers. This variation deviates the design parameter from specific values and degrades the performance. Process, voltage, and temperature (PVT) variations are uncontrollable natural occurring phenomena during fabrication steps that result in slow and fast MOS transistors. In this paper effect of variability on the performance of the nonlinear cryptographic block substitution box (SBOX) is explored at CMOS 45 nm technology at 1 V supply voltage. Performance parameter optimizes by including underlying cells with different CMOS logic structures like pass transistor logic (PTL) and transmission gate (TG). Power consumption pattern increases with FF corner and decreases towards the SS corner while delay varies differently for SF and FS corner. SBOX underlying cell XOR & AND gate implemented with PTL logic reduces the transistor count and lowers power consumption but at the same time PTL logic enhances delay. For the SBOX with TG logic decreases delay by maintaining power and area under specific limit. Delay and power vary more rapidly for PTL, and TG logic compares to static CMOS logic. The simulation result justifies that voltage and temperature variation is more pronounced at SF and FS corners compared to others. Maximum variation occurs for the delay, at SF corner with − 10% supply variation 307.52% and power at FS corner with + 10% supply variation 99.81%. The process variability of SBOX is majorly oriented towards the cryptographic applications and to access the SBOX vulnerabilities and countermeasures challenges.

Implementation of High Performance 4-Bit ALU using Dual Mode Pass Transistor Logic

Abstract: In this paper, we present a four bit arithmetic logic unit which is energy efficient and temperature invariant implemented using the dual mode pass transistor logic. The basic logic gates such as NOR and NAND are designed using both CMOS logic and dual mode pass transistor logic and are used in the proposed design. Simulations performed demonstrated that DMPL can reduce the computed worst case delay by 42.39%and 39.13%for NOR and NAND gates respectively in dynamic mode and average power dissipation by 67.96%and 24.09%for NOR and NAND gates respectively in static mode. In the implemented Arithmetic and Logic Unit, we observe a reduction in worst case delay and average power dissipation by 62.67%and 28.28%. The proposed logic was implemented in 90nm bulk technology using Cadence® Virtuoso® Schematic Editor.

Design of Current Mode MOS Logic for Low-Power Digital Applications

Abstract: Today, the major limitation of designing of high-speed integrated circuits (ICs) with conventional technology is the delay limiting the switching speed of the gates As evident from already established logic styles like complementary pass transistor logic (CPL), differential cascode voltage swing logic (DCVSL), etc, the circuit exploits the property of noise reduction due to differential inputs Ideally current mode circuits have constant current gain with no input impedance and finite output impedance The current gain of the circuit is set to unity as current amplification leads to higher consumption of static power MOS current mode logic (MCML) is graced with certain advantages which include low level of noise generation, static power dissipation independent of switching activity, low voltage swing, a weak dependence of propagation delay on fan-out load capacitance, lower power dissipation at higher frequencies, etc, out way the few disadvantages such as elaborated design process and increased number of design parameters In this paper, we present an in-depth study of MCML base approach in which the analysis of low-power applications is performed at the target data rate of 1 Gbps Work has been done on a standard CMOS technology of 018 μm

Low Power and Area Efficieny ALU With Different Type of Low Power in Full Adders

Abstract: This paper presents a low power area efficient of a ALU using different low power full adders. Classified as XNOR logic, pass transistor, 2T XOR logic. The 4-bit ALU design is compared with respect in their power consumption and area. ALU is an operating system named as Arithmetic and Logic Unit, which perform arithmetic operation like ADD, SUB, PASS THROUGH TWO'S COMPLEMENT etc. and logic operation like AND,OR,EXCULSIVE OR,EXCLUSIVE NOR etc. We introduce different types of full adders, which are taken as 6T XNOR logic, 6T 2t XOR Logic and pass transistors using 6T to produce sum and multiplexers are used for carry. Full adder is a part of an ALU, it can be used with varying Transistors. By reducing full adder power, we can reduce the power of ALU. Compared with existing technique power can be decreased by <50% by changing full adders. The simulation is carried in cadence virtuoso 90nm technology. Compared with the previous design of gate diffusion input, the results shows area efficient and low power with existing work.

Design and implementation of reversible logic gates using silicene-based p–n junction logic devices

Abstract: Advancements in adiabatic quantum computing have enabled a rapid development in thermodynamically reversible logic circuits, which can reduce energy wastage to almost negligible levels. Various reversible logic gates using silicene-based multiplexer logic devices (SMLDs) are designed and demonstrated herein using Verilog-A, then validated by SPICE circuit simulations. The results confirm that the various reversible gates correctly implement the corresponding truth tables, thereby validating the use of SMLDs as building blocks for such gates. The SMLD-based reversible logic gate designs enable a reduction in hardware complexity by 76.92–80.64% compared with complementary metal–oxide–semiconductor (CMOS) technology and a 50% reduction in hardware compared with pass transistor logic-based designs, respectively.

Exploration of logic gates and multiplexer using doping-free bipolar junction transistor

Abstract: Logic gates are designed using symmetric lateral doping-free bipolar junction transistor (BJT) on silicon on insulator (SOI) using differential pass transistor logic, and their performance matrices are presented. Charge carriers are induced in lightly doped emitter and collector regions using two unique approaches. i.e., the charge plasma (CP) and polarity control (PC). AND, OR and XOR gates are designed using four types of devices (CP-NPN, CP-PNP, PC-NPN, and PC-PNP) and transient and noise margin analysis are performed. The transient response shows rise and fall time less than 100 ps while worst-case noise margin of 0.25 V observed for an input voltage of 1 V. Moreover, 2:1 multiplexer is also designed and explored for output transient and voltage levels. The delay of less than 2.2 ns is achieved with a nominal deviation of 0.1 V and 0.04 V for high and low output levels respectively.

Performance Analysis of a Low Power High Speed Hybrid Full Adder Circuit and Full Subtractor Circuit

Abstract: In this paper, a hybrid 1-bit adder and 1-bit Subtractor designs are implemented. The hybrid adder circuit is constructed using CMOS (complementary metal oxide semiconductor) logic along with pass transistor logic. The design can be extended 16 and 32 bits lately. The proposed full adder circuit is compared with the existing conventional adders in terms of power, delay and area in order to obtain a better circuit that serves the present day needs of people. The existing 1-bit hybrid adder uses EXNOR logic combined with the transmission gate logic. For a supply voltage of 1.8V the average power consumption (4.1563 µW) which is extremely low with moderately low delay (224 ps) resulting because of the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. At 1.2V supply the power and delay were recorded to be 1.17664 µW and 91.3 ps. The design was implemented using 1-bit which can also be extended into a 32-bit design later. The designed implementation offers a better performance in terms of power and speed compared to the existing full adder design styles. The circuits were implemented in DSCH2 and Microwind tools respectively. The parameters such as power, delay, layout area and speed of the proposed circuit design is compared with pass transistor logic, adiabatic logic, transmission gate adder and so on. The circuit is also designed with a decrease in transistors in order to get the better results. Full Subtractor, a combinational digital circuit which performs 1-bit subtraction with borrow in is designed as a part of this project. The main aim behind this part of the project is to design a 1-bit full Subtractor using CMOS technology with reduced number of transistors and hence the efficiency in terms of area, power and speed have been calculated is designed using 8,10,15and 16 transistors. The parameters were calculated in each case and the results have been tabulated.

A PTL based power efficient ALU block using 45nm Technology

Abstract: Pass Transistor Logic is one of the best among the available methods to implement circuits where low power plays a major role. This logic nullifies the leakage power in total power consumed by the circuit. This paper deals with the design of 4-Bit ALU. The proposed ALU is capable of performing AND, OR, XNOR, XOR, Sum, Carry operations of two 4-Bit binary numbers. A 4-Bit adder is designed by cascading Half-adder and Full-adder circuits to obtain sum, carry. For the purpose of selecting the desired operation 8:1 Multiplexers are used. The simulation result consists of power calculated for 4-Bit ALU,1-Bit Logical Block, Multiplexers. For the simulation of the circuits we have used virtuoso platform of Cadence tool with 45nm CMOS technology and supply voltage of 1V.

FPGA Realization of the Reconfigurable Mesh Counting Algorithm

Abstract: Pass transistor logic (PTL) is a circuit design technique wherein transistors are used as switches. The reconfigurable mesh (RM) is a model that exploits the power of PTLs signal switching, by enab...

Comparative Analysis of Adder for Various CMOS Technologies

Abstract: The current technologies are moving towards small size, high speed, and cost-effective computing systems. The demand of efficient devices such as operating at high speed and low power is always increasing. Therefore, the work compares various design configuration to check their performance. Adders are the key element of the arithmetic functions such as addition, multiplication, subtraction, and division. Adder has been simulated using spice code to check their functionality. Synopsis HSPICE simulator is used to analyze the circuits for various CMOS technologies. The proposed pseudo domino techniques are proffered to economize power dissipation up to 61% in half adder circuit and 32% in full adder circuit. The 14 transistor based design is economized the power dissipation up to 60% in 1-bit adder circuit.

Memristor-based Pass Gate Targeting FPGA Look-Up Table

Abstract: This work proposes a memristor-based Pass Gate - mPG, as a primitive cell for translating memristor resistance states into logic targeting for FPGA Look-Up Tables (LUTs). The mPG consists of a pass transistor with buffers, and it can work with both binary and multibit memristors. The utilization of mPGs for the configuration bit storage in a new LUT architecture based on multibit memristors is introduced. Unlike other prior structures, the proposed architecture not only eliminates leakage current and extra sense amplifier/comparator circuitry but also prevents degrading memristor's characteristics; thus, more reliable systems can be developed. Simulation results show that the gate can be deployed for a wide range of memristor's resistance with a switching delay in the nanosecond range. Physical implementations of multibit memristor-based LUTs demonstrate that up to 80% of the design area and/or the number of transistors could be saved in comparison to standard SRAM-based designs. Furthermore, mPG-based design considerations are thoroughly analyzed and presented.

Design and Optimization of 4-bit Absolute-value Comparator Using CMOS & PTL Technique

Abstract: In recent years, a rapid technological progress has been going on in the electronic industry, the level of integration and chip manufacturing process made significant progress within a few years' time. This causes a growing demand for swift and reliable devices design with low energy consumption. To achieve this goal, parameters like power dissipation and delay which are important roles of modern electronic device manufacturers have to be considered. In the paper, a hybrid design of a 4-bit absolute-value detector with the ability to compare the value of two inputs represented in 2‘s complement format is being done using Static CMOS logic, Pass Transistor Logic (PTL) and Transmission Gate Logic (TGL). The design uses the hybrid design described above to simplify the circuit and find a specific logic, especially for the absolute-value detect function, to reduce transistors. In order to prevent unexpected delays caused by the huge capacitive load driven at the output end, the design adopts an inverter chain as a buffer to avoid this situation. Based on the logic effort theory, this work transforms the capacitance and resistance of each gate into a ratio to a unit size inverter to find the total delay and energy consumption after locating the critical path. This study employs transistor sizing and power source (VDD) scaling technique to optimize the delay and energy consumption of the circuit towards different optimization goals (minimum delay or minimum energy with a delay less than 1.5 times of the minimum delay). These optimization strategies are simulated by MATLAB and LTSPICE software. The delay or energy consumption are represented by a ratio to that of a unit size inverter, then compared in the paper. A great improvement in the circuit performance has been shown in all optimization strategies, proving them to be practical and efficient designs for future use.

A Power Management System Based on Adaptive Low-Dropout Voltage Regulator with Optimal Reference Pre-Compensation Technique

Abstract: This paper presents an adaptive dropout voltage regulator based on a constant on-time buck converter that improves the light load efficiency. By regulating the gate voltage of the pass transistor of the low dropout regulator (LDO), the dropout voltage is automatically minimized depending on the load current, increasing the end-to-end power conversion efficiency at the light load condition by 11.3%. The proposed direct-charging scheme and simple undershoot detector reduce the droop and improve the efficiency of the LDO. The reference pre-compensation technique is proposed to improve the ripple performance by compensating the reference voltage based on the on-time pulses. The proposed voltage regulator was fabricated by a 0.18-wm CMOS process and occupies 0.2874 mm2.

Adiabatic Technique Usage for the Analysis of Power Dissipation in Logic Gates

Abstract: Adiabatic circuits are low power circuits, which oversees the reversible method of reasoning that it stores the power and gives it back again. At present Several Adiabatic methodologies have been gotten for viable power dispersal. The system used to restrain control dispersing are Efficient Charge Recovery Logic, Positive Feedback Adiabatic Logic, and Pass Transistor Logic. The Adiabatic method is essentially cast-off for decreasing the influence dissipating in VLSI tracks, which does indict and squaring system. The method of reasoning doors accepts a critical activity in various number shuffling assignments, for instance, the twisted, multiplier, divider and processors. To compile the power spread, a profitable full adder proposed for the particular adiabatic methods, and all of the circuits have been simulated by 25nm innovation utilizing the tanner EDA tool.

A Split-Input Driver-Enabled High-Speed and Energy-Efficient Level Shifter Using Hybrid Pull-Up Network

Abstract: Level shifters are the prominent interfacing circuits used in VLSI systems involving multiple supply voltages for their energy-efficient operation. The hybrid pull-up network (HPN)-based level shifter (HPLS) with an enhanced speed and energy performance is proposed in this paper that minimizes the voltage drop and current contention issue prevalent in the prior art. The HPN comprises the cross-coupled PMOS and the current mirror structure to improve the standby power performance. The proposed HPLS utilizes a split-input driver as an output stage to achieve both the area and energy efficiency. In addition, the usage of a pass transistor in the pull-down network enhances the speed performance by decreasing the rise/fall times. The performance of HPLS is verified by implementing it in CMOS 180 nm technology using Cadence tool and simulated through Spectre circuit simulator. The simulation results of the HPLS reveal 9.6 ns of delay and 66.77 fJ of energy consumption for the applied input signal of 0.4 V/1 MHz with 1.8 V high supply voltage. Further, it consumes smaller static power of 0.82 nW and occupies silicon area of 204 $$\upmu $$ m $$^{2}$$ (12 $$\upmu $$ m $$\times $$ 17 $$\upmu $$ m).

Low drop-out regulator (ldo)

Abstract: Regulation/Bypass automation for a low drop-out regulator (LDO) with multiple supply voltages is disclosed. In some implementations, a LDO includes a resistor, a pass transistor having a source, a gate, and a drain to output a voltage Vout, the source coupled to a supply voltage, the gate coupled to an output of an operational transconductance amplifier (OTA), and the drain coupled to a first terminal of the resistor; a feedback switch having a drain, a gate, and a source, the drain coupled to a second terminal of the resistor, the source coupled to a negative input of the OTA; and an pull-down transistor having a drain, a gate, and a source, the source coupled to ground, and the drain coupled to the negative input of the OTA, wherein the gate of the pull-down transistor and the gate of the feedback switch are configured to receive a bypass signal.

Adiabatic Logic-Based Area- and Energy-Efficient Full Adder Design

Abstract: Low energy- and area-efficient digital circuit design is unique among the significant navigational challenges of digital VLSI design suitable for real-time applications. Full adders are essential functional elements in complex arithmetic circuits; a 1-bit adder is developed by using adiabatic logic in this operation to get low power consumption. The intended 1-bit adder cell with adiabatic logic results in very less heat dissipation with its surrounding circuit atmosphere. As a result, this logic has minimal energy loss due to overheating dissipation. The proposed adiabatic logic circuit is compared with CMOS and pass transistor logic (PTL) with TG 1-bit adder topologies. The results show that there are significant advantages in power saving compared to CMOS and pass transistor cells. The proposed adiabatic logic full adder requires 18 transistors to design. The proposed adiabatic logic 1-bit adder, designed with three inputs, produces the output response as true and complementary outputs in a single architecture. All full adder cells were designed with 65 nm technology and compared area and power consumption.

UBAPS: Inexact Unsigned Binary 5:2 Compressor Towards Power Efficient and High Speed for Three-Stage FIR Filter

Abstract: An efficient multiplier is one of the crucial modules in many of the digital circuits, entailing its prominence in many applications of VLSI such as digital signal processing, cryptography, and communications. With the advancement of technology, circuits have been enforced to encounter the power, area constraint, and propagation delay parameters. In this regard, compressors have become imperative, forming the elementary part of multipliers in reducing and associating the partial products in a parallel way. In this paper, a 5:2 compressor is proposed with abridged power consumption and propagation delay factor. Approximate compressors with synthesizable structural reductions have led to better results, subsequently higher-order multipliers, filters are constructed with simpler and higher-order compressors. Using 45 nm technology, the design has been implemented in pass transistor logic (PTL), where the speed has escalated by 98.4%, power improvement of 78.04%, compared to the other compressor design in the literature.