Showing papers on "Physical design published in 1987"

IDAC: an interactive design tool for analog CMOS circuits

Abstract: A design system has been developed which is able to design transconductance amplifiers, operational amplifiers, low-noise BIMOS amplifiers, voltage and current references, quartz oscillators, comparators, and oversampled A/D converters including their digital decimation filter starting from building-block and technology specifications. This design system, called Interactive Design for Analog Circuits (IDAC), is able to size a library of analog schematics (actually more than 40) as a function of technology (p-well and n-well CMOS) and desired building-block specifications. IDAC also generates a complete data sheet, an input file for SPICE2, and an input file for the analog layout program ILAC.

A modular user-oriented decision support for physical database design

Abstract: A decision support package for the design of indexes in a relational database environment is presented. It originates from the theoretical results collected inside the DATAID methodology. Its main features are a high level language user interface, an incremental description of the design environment, a forecasting of the execution I/O costs if the proposed solution is adopted and also a guidance for the access paths to be selected in the various operations.

Integrated circuit packaging configuration for rapid customized design and unique test capability

Abstract: The present invention employs a high density interconnect method to take advantage of a packaging arrangement in which full customization of an integrated circuit chip package is providable in a single metallization layer. The integrated circuit chips are positioned to take full advantage of a wiring layer which includes a plurality of periodically interrupted conductor patterns. All of the customization is provided in a single layer which may be readily fabricated and produced in a single day making it possible for extremely rapid turn around time in the design of complex integrated circuit systems, particularly those constructed from readily available integrated circuit components including microprocessors, random access memory chips, decoders and the like. An integrated circuit is also disclosed for fully taking advantage of the capabilities of testing made available by the high density interconnect system.

Method for physical VLSI-chip design

Abstract: For the physical design of a very large scale integration (VSLI) chip, a method is provided to implement a high density master image that contains logic and RAMs. In a hierarchical top-down design methodology, the circuitry to be contained on the chip is logically divided into partitions that are manageable by the present automatic design systems and programs. Global wiring connection lines are from the beginning included into the design of the different individual partitions and treated there in the same way as circuits in that area. Thus, the different partitions are designed in parallel. A floor plan is established that gives the different partitions a shape in such a way that they fit together without leaving any space between the different individual partitions. The chip need no extra space for global wiring and the partitions are immediately attached to each other. The master image described is very flexible with respect to logic, RAM, ROM and other macros, and it offers some of the advantages of semicustom gate arrays and custom macro design. The thus designed chip shows no global wiring avenues between the partitions and has partitions of different porosity.

Expert systems for mechanical design: Examples of symbolic representations of design geometries

Abstract: A major issue in the development of computer-integrated manufacturing systems is the creation and maintenance of a suitable data base that will serveall the various functions in the design through manufacturing sequence. These functions include the designer interface, graphics output, evaluation of manufacturability, functional evaluation (including possibly finite element analyses), process design, process planning, process control, and quality control. Since design is the beginning of this design manufacturing spectrum, it is incumbent on the design process to produce the required data structure that will allow input and access by the other functions. A key element in such a multipurpose data base is the method by which the design geometry is represented, and an essential ingredient of this representation is information about the geometricfeatures of the design that are relevant to the various parts of the sequence. We are exploring “design with features” as a design method to obtain the needed feature information and experimenting with different data structures for symbolic representation of the resulting designs. In this paper, we describe three examples of different types of features for use as design primitives and four data structures (in LISP) that result from their use. The domains of the examples are extrusion, injection molding, and casting.

Benchmarks for Cell-Based Layout Systems

Abstract: Introduction Cell-based layout systems are widely used for automatic physical design of large digital systems. Standard cell and gate array layout systems are reaching a state of maturity: small differences in layout effectiveness are used to distinguish commercially available systems. General cell and mixed standard cell and general cell layout systems have moved from research projects to general availability. Even with this widespread use and the many publications of cell-based layout systems, no recognized benchmarks are available to form the basis of comparison and evaluation. In addition to the difficulty of comparing layout systems, algorithm research is hampered by the lack of recognized benchmark examples. It is very difficult to evaluate published algorithms because common examples are not used. Potentially promising algorithms have been denied publication because some researchers do not have access to real circuit descriptions. Random or contrived examples are, to a large number of reviewers, no longer acceptable for journal and conference publication. For some problems, publication of examples is sufficient to establish industry wide benchmarks; channel and switchbox routing are examples. However, cell-based layout problems are much too complex for such casual methods. Practical circuits may have several thousand cells, and circuits with over 10,000 cells are reported with some regularity. For such circuits, the parts list and the interconnection list may require a substantial fraction of a megabyte for storage. In addition to large size, the complexity of the cell libraries and the design rules inhibit sharing of layout examples. This panel wiH consider the benefits, problems and challenges of creating, distributing and maintaining a representative set of benchmarks for cell-based layout systems.

Design And Test of the 80386

Abstract: A complex design effort, the 80386 was nevertheless one of the company's most successful projects. The work was completed in less time than scheduled and set an Intel record for tapeout to mask fabricator. The strategy incorporated both top-down and bottom-up design approaches. The top-down flow was external architectural definition, internal architecture, internal unit RTL (register transfer logic) and finally detailed logic. The bottom-up flow was detailed transistor and cell circuit design and layout, block (ALU, PLA, etc.) circuit design and layout, and finally global circuit design and layout. Testability also played an important part in the design's success. The 80386 combines two forms of designed-in test functions: built-in self-test and test hooks or functions explicitly designed in to aid testing.

Performance-Oriented Synthesis of Large-Scale Domino CMOS Circuits

Abstract: The quality of the design of large-scale integrated circuits is determined by such figures of merit as silicon area, power consumption, and switching-time performance. We address here the problem of the automatic synthesis of digital circuits with the goal of achieving high-performance designs. We assume we are given an intermediate circuit representation that optimizes area and/or power. We use timing optimization techniques to improve the circuit performance, possibly at the expense of the other figures of merit. We consider general classes of digital circuits, with a given partition into registers, combinational blocks, and I/O ports. Circuit performance is related to the worst-case propagation delay of signals between two register boundaries. In this context, circuit performance optimization is equivalent to minimizing the critical path delay through the combinational circuits. We assume a multiple-level implementation of the combinational logic, by means of an interconnection of logic gates implementing arbitrary multiple-input, single-output logic functions. We consider dynamic CMOS implementation of the logic gates, operating in the domino mode. We present a global approach to timing performance optimization, which involves operations at the logic, topological, and physical level of abstraction of the circuit. In particular, at the logic level, we look for optimal structures of multiple-level combinational networks. At the topological level, we search for the optimal positions of gates or groups of gates. At the physical design level, we optimize MOS device sizes. The algorithms are described, together with their implementation and the interface to the Yorktown Silicon Compiler system, which is an automated synthesis system described in [7]. The results of applying timing-performance optimization to a 32-bit microprocessor design are reported.

A Hierarchical Approach to Test Vector Generation

Abstract: Given a combinational network and a specific stuck-at fault to be detected, there are several approaches to generating a test vector However, most of these approaches fail to exploit the hierarchy inherent in any complex digital design This paper presents a hierarchical approach to test vector generation HIPODEM: A test generation system based on this approach is presented General procedures to perform forward implication and backtracing in a hierarchical framework are discussed in detail Experimental results obtained from test runs on both flat-level and hierarchical circuits are compared For the circuits tried, generating tests from a hierarchical description proved to be faster than doing it from a flat level description of the circuit

Easily testable semiconductor LSI device

Abstract: In a large scale integrated (LSI) circuit, a through-passage circuit together with a selector circuit is provided between an input circuit and an output circuit, thereby enabling to selectively short-circuit the input circuit to the output circuit. In testing a complex circuit including two or more such LSIs, the internal circuit of the LSIs can be selectively extremely simplified to enable easy and fast testing.

CMOS VLSI Applications in Broadband Circuit Switching

Abstract: The circuit switching fabric for broadband networks will demand numerous densely interconnected components, with channel rates as high as 150 Mbit/s, This is a natural application area for VLSI, which motivates the evaluation of the key technologies and requirements for realizable broadband circuit and packet switching systems. The critical circuit switching capabilities include the basic crosspoint array, I/O interface between circuit packs, jitter removal and regeneration, and multichannel phase alignment. This paper describes results obtained in these four critical areas. With remote multiplexing units, the greatest constraints are power dissipation and system volume. CMOS circuitry has the advantage here, because of its intrinsic usage-sensitive low power operation. The challenge is to prove that CMOS processes and designs are compatible with the high data and clock rates required of broadband ISDN systems. A fully connected 16 × 16 crosspoint array has been implemented by several laboratories. In this paper we will report on our asynchronous 16 × 16 switching chips fabricated in a 2 μm CMOS process. These devices support channel rates of up to 240 Mbit/s. Crosstalk, jitter accumulation, and power dissipation dominate system issues at the IC interface, making simple CMOS or TTL signaling inappropriate for broadband applications. We will discuss the ECL compatible signaling used in our broadband CMOS IC's. This low noise interface is currently operating at 150-200 MHz rates. We will stress the resulting improvement in noise and jitter accumulation. We will also consider a broader class of low power signaling schemes, including CMOS to GaAsFET direct interfacing. The physical design of switching fabric components will be at least as important as the electronics. Our custom high-density chip carrier and surface mounting arrangement will be discussed, which offers a fourfold reduction in parasitic inductance and capacitance, with corresponding reductions in crosstalk, jitter, and interconnect power dissipation. Pulses normally degrade after passing through asynchronous crosspoint elements. A scalable switching fabric must include regeneration to control this accumulated noise and jitter. We have demonstrated the critical components of such a regenerator, including VCO's, process independent digital phase shifters, phase error detectors, and data relocking circuitry. Existing CMOS technology can support the circuit switching requirements for broadband networks. A thorough understanding of the interface capabilities and requirements will be necessary to deliver functional hardware. The knowledge gained in this work will have direct application to packet switch constraints and performance.

A Model for Wafer Fabrication Dynamics in Integrated Circuit Manufacturing

Abstract: Integrated circuit manufacturing has major operations of fabrication, sort, assembly, and test. The dynamic behavior of these operations can be modeled in terms of a highly structured queueing network. A model is presented of the components and interactions of wafer movements, processing equipment, and process steps. The model considers multiple process flows, fab organization and layout, and equipment properties such as batch size, process time, failure, and repair distributions. The model is implemented as a discrete event simulation and has been used in a number of case studies concerning realistic factory situations. This simulation model is general and can be used to study many types of discrete manufacturing.

3-input Exclusive-OR gate circuit

Abstract: The present invention is an Exclusive-OR circuit which uses a minimum number of components and which is particularly adapted for use as a building block for a parity checking circuit. The circuit only uses CMOS gates to reduce the number of included transistors.

Fast Methods for Switch-Level Verification of MOS Circuits

Abstract: Simulation of hardware is a commonly-used method for demonstrating that a circuit design will work for a restricted set of inputs. Verification is a method of proving a circuit design will work for all combinations of input values. Switch-level verification works directly from the circuit netlist. The performance of existing switch-level verifiers has been improved through a combination of techniques. First, efficient methods of finding paths in the switch-graph are developed. Secondly, static analysis of the switch-graph is proposed to accelerate verification of sequential logic. Thirdly, cell replication is exploited in a safe way to make possible the verification of large hierarchical circuit designs. These ideas have been implemented in a program called V, which is part of the Penn State Design System. Experimental results are presented.

Compilation of standard-cell libraries

Abstract: The compilation approach used to generate and verify a complete standard-cell library is presented. Each standard cell is comprised of layout, a behavioral model, and documentation. The tradeoffs are described and this approach is compared to traditional methods. This approach allows rapid generation of complete libraries regardless of technology. Furthermore, improvements and fixes are rapidly incorporated into an entire library. Over 280 standard cells were created by five people in nine months.

A computer-aided design and simulation tool for switching converters

Abstract: A fully automated computer-aided design approach is presented which results in an optimal power stage and control circuit design. The design meets all dc, small signal and large signal closed-loop performance specifications. The proposed approach is very efficient; it can help in reducing component and manufacturing costs as well as design time and is successfully demonstrated on a multiple-output flyback converter breadboard.

ESKISS : a program for optimal state assignment

Abstract: • A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication

Method and apparatus for verifying proper placement of integrated circuits on circuit boards

Abstract: In order to determine whether the proper type of integrated circuit is located in the proper position (16) and the proper orientation, a power source (18) applies a potential difference to circuit paths (26 and 28) that will properly power an integrated circuit (14) if it is of the proper type and in the proper orientation. Without attempting to place the integrated circuit (14) in a predetermined state, a test system (10) employs a milliammeter (32) first to measure the current driven by an output terminal (30) and then to measure the current that the output terminal (30) draws from a bias source (40). If a current level consistent with an active output terminal is measured in either step, a control circuit (38) concludes that the integrated circuit (14) is of the proper type and properly positioned. Otherwise, the control circuit (38) concludes that an integrated circuit is missing, of the wrong type, or improperly oriented. The test is thus performed with power applied to the integrated circuit so that the test can be based on reliable circuit parameters, but the damage that might otherwise result from a powered-up test is avoided because, since no time is expended in conditioning the integrated circuit to a predetermined state, the test can be made extremely short in duration.

A Rule-Based Circuit Representation for Automated CMOS Design and Verification

Abstract: A novel rule-based circuit representation is proposed to describe the connectivities of CMOS circuits at the transistor level. The unique feature of the rule-based representation is its ability to automate CMOS circuit design and verification. A precise symbolic description of the functionality of a transistor-level circuit can be derived based on a set of production rules in linear time. Automated synthesis and verification of CMOS logic circuits are demonstrated.

Design of a Process Tolerant Cell Library for Regular Structures using Symbolic Layout and Hierarchical Compaction

Abstract: A method is presented to design cell libraries, using a symbolic layout editor and a hierarchical compaction algorithm with automatic terminal fitting. In contrast to language based procedural layout, this technique guarantees correctness and easy updatability to new circuit techniques and layout rules. It can be applied to all regular hierarchical layout structures where constrained cells have to be designed. Once the library is established it can be used over and over again with different personality matrices for fast generation of correct layout.

Semiconductor integrated circuit with a test function

Abstract: A semiconductor integrated circuit comprises a plurality of integrated circuit blocks (31 - 39) constituted on a wafer (30), the integrated circuit blocks being arbitrarily electrically connected to each other so as to form a system. Each of the integrated circuit blocks comprises a logical operating circuit (42) for carrying out a logical operation; a pseudo-random pattern generating circuit (40) for generating a pseudo-random pattern signal; switching circuit (41) for selecting either an input signal to be processed by the logical operating circuit or the pseudo-random pattern signal in response to a test enabling signal (TE1 - TE9) which is independently applied to each integrated circuit block so that each integrated circuit block is independently set to either a test mode or a normal mode and for outputting the selected signal to the logical operating circuit; and a data compressing circuit (43) for compressing an output data signal of the logical operating circuit.

TRIP: An Automated Technology Mapping System

Abstract: A technology mapping system, used for computer design in NEC, is presented. The features of this system are technology conversion and logical/physical optimization, based on a rule base, partitioning support, conversion verification and special layout consideration. This system is practically used for many applications for technology mapping, including redesigning an existing total unit into a new unit, based on up-to-date LSI technology. The resulting effect is quick inputting of integrated circuit technology progress into practical computer design area.

Report: Systems packaging

Abstract: The packaging of an electronic system is the translation of the system designer's concepts into physical realities. Packaging is a major engineering consideration which addresses every element in the system's makeup, from the fundamental material and circuit technologies to manufacturing and final testing strategies. The packaging scheme implemented for a particular system is termed its physical design. The physical design process is descriptive of the methods used to “package” an electronic system.

Structured arithmetic tiling of integrated circuits

Abstract: Robertson's Theory of Decomposition and Structured Tiling (an IC design technique) are combined in a structured arithmetic circuit design method. This method, extended by a set of inverse operators and a set of multiply operators, is used with computer-aided design tools to automate the design of arithmetic circuits.

Enhancing the transfer of inductive energy to imploding plasma loads with a single-step meatgrinder circuit

Abstract: The transfer of magnetic energy to an uncoupled load inductor using a novel inductive storage and transfer circuit (single-step meatgrinder) is compared with two classical inductive circuits. The first is the inductor-inductor transfer via an opening switch. The second is a transformer circuit where the primary circuit is opened and energy is transfered to the secondary and the uncoupled load. For identical loads the new circuit is shown to provide a 90-percent improvement over the two conventional circuits in energy transferred to the uncoupled load. A low-current low-voltage experiment, where 35.4 percent of the initial inductive energy is transferred to an uncoupled load using the new circuit, is discussed. A physical design for the Air Force Weapons Laboratory Shiva bank, which accounts for voltage holding, coupling, and parasitic inductance in the switches, is also described.

Affordable dwelling-layout system design—A model for optimization

Abstract: The systems nature of the residential land planning has been outlined and an optimization model for minimizing the cost of a layout has been presented earlier. In the present paper, a model for optimal design of the dwelling-layout system, consisting of the dwelling as well as the residential layout, has been developed. In this model, which is also a non-linear programming problem, maximizing the dwelling space has been taken as the objective function. Affordable cost and physical design standards such as density, public open space, circulation interval, have been taken as the constraints in the model. The problem has been solved using the geometric programming technique and the programme developed by the author. Using this model, a dwelling-layout system could be designed directly to achieve the maximum benefit i.e. maximum dwelling space, within the given affordable cost and fulfilling the given physical design standards mentioned above.

Compaction-Based Custom LSI Layout Design Method

Abstract: This paper presents a new design method for custom LSI layouts. This method is based on layout compaction with automatic jog (wiring bend) generation in the layout. A dense chip design can be realized by this technique. Experimental results show that the chip size designed by using the proposed layout method is only 1.2-1.4 times larger than that resulting from manual layouts. Therefore, this compaction-based custom LSI layout design method is very effective for achieving a minimal chip layout design.