Showing papers on "Polysilicon depletion effect published in 1994"

Nonvolatile semiconductor device having charge trap film containing silicon crystal grains

Abstract: A tunnel oxide film 12 is formed on a silicon substrate 11 and a polysilicon film 16 is deposited thereon. Then, an impurity such as phosphorus or the like is doped into the polysilicon film 16 and the polysilicon film 16 is subjected to thermal oxidation. As a result, a charge trap film 15 in which silicon grains 13 in the inside of the polysilicon film 16 are coated with a thermal oxide film 14 is obtained. If necessary, a multilayer charge trap film 15 is obtained by repetition of the foregoing steps. Since the thermal oxide film 14 has an excellent insulating property compared with an oxide film obtained by a sputtering or CVD method and therefore the charge trap film 15 has a high dielectric withstanding voltage. Further, since the silicon grains 13 coated with the thermal oxide film 14 have a deep trap level, an improved signal charge holding property can be obtained. Thereby, it is provided a nonvolatile semiconductor storage device comprising a charge trap film having a deep trap level and an improved dielectric withstanding voltage.

Method for forming a vertical transistor with a stacked capacitor DRAM cell

Abstract: There is shown a method for fabricating a vertical DRAM cell which includes a field effect transistor having a gate electrode and source/drain elements and a capacitor. There is provided a pattern of field oxide isolation in a silicon substrate wherein there are a pattern of openings to the silicon substrate. A pattern is formed of bit lines and a pattern of lines of holes with a hole located within each of the openings to said silicon substrate which lines of holes and bit lines are perpendicular to one another and which the lines cross at the planned locations of the vertical DRAM cell at the pattern of openings to the silicon substrate. A gate dielectric is formed on the surfaces of the holes. A doped polysilicon layer is formed in and over the holes so that it covers the gate dielectric and the field oxide isolation. A silicon nitride layer is formed over the doped polysilicon layer. Patterning and etching is done to the silicon nitride layer and doped polysilicon layer to form the opening for the capacitor node contact to the buried source/drain of the vertical field effect transistor (switching device for the storage signal) and establish said gate electrode in the hole and word line pattern over the field oxide insulator. A silicon oxide spacer is formed over the sidewalls of the silicon nitride and doped polysilicon layer. A capacitor is formed in and over the hole to complete the vertical DRAM cell.

Porous polycrystalline silicon: a new material for MEMS

Abstract: A new technique for the fabrication of thin patterned layers of porous polycrystalline silicon (polysilicon) and surface micromachined structures is presented. First, a multilayer structure of polysilicon between two layers of low-stress silicon nitride is prepared on a wafer of silicon. Electrochemical anodization with an external cathode takes place in an RF solution. A window in the outer nitride layer provides contact between the polysilicon and the HF solution; the polysilicon layer contacts the substrate through openings in the lower silicon nitride layer (remote from the upper windows). Porous polysilicon growth in the lateral direction is found at rates as high as 15 /spl mu/m min/sup -1/ in 12M (25%, wgt) HF to be controlled by surface-reaction kinetics. A change in morphology occurs when either the anodic potential is raised or the HF concentration is decreased, causing the polysilicon to be electropolished. The etch front advances proportionally to the square root of time as expected for a mass-transport-controlled process. Similar behavior is observed in HF anodic reactions of single-crystal silicon. Dissolution of the polysilicon layer is confirmed using profilometry and scanning electron microscopy. Enclosed cavities (chambers surrounded by porous plugs) are formed by alternating between pore formation and uniform dissolution. Porous polysilicon also forms over a broad-area layer of polycrystalline silicon that has been deposited without overcoating the silicon wafer with a thin film of silicon nitride. The resulting porous layer may be useful for gas-absorption purposes in ultrasonic sensors. >

Diamond shaped gate mesh for cellular MOS transistor array

Abstract: A cellular transistor structure is disclosed which incorporates a polysilicon gate mesh. In one embodiment, the silicon under the polysilicon is of an N-type while the exposed area a not covered by the polysilicon is doped with a P dopant to form P-type source and drain regions. Metal strips are used to contact the rows of source and drain cells. By forming the openings in the polysilicon mesh to be in a diamond shape (i.e., having a long diagonal and a short diagonal), the source and drain metal strips, arranged in the direction of the short diagnonals, can be made wider and shorter, thus reducing the on-resistance of the transistor without increasing the area of the transistor.

Method of making a diamond shaped gate mesh for cellular MOS transistor array

Abstract: A cellular transistor structure is disclosed which incorporates a polysilicon gate mesh. In one embodiment, the silicon under the polysilicon is of an N-type while the exposed area not covered by the polysilicon is doped with a P dopant to form P-type source and drain regions. Metal strips are used to contact the rows of source and drain cells. By forming the openings in the polysilicon mesh to be in a diamond shape (i.e., having a long diagonal and a short diagonal), the source and drain metal strips, arranged in the direction of the short diagonals, can be made wider and shorter, thus reducing the on-resistance of the transistor without increasing the area of the transistor.

Method of fabricating semiconductor device having polysilicon resistor with low temperature coefficient

Abstract: A semiconductor device having a p type polysilicon resistor (56) with a moderate sheet resistance and low temperature coefficient of resistance is formed by a double-level polysilicon process. The process also produces n and p-channel transistors (44, 50), a capacitor having upper and lower n type polysilicon capacitor plates (36, 26), an n type polysilicon resistor (32) having a high sheet resistance, and an n type resistor (34) having a low sheet resistance. The p type doping used to form the source/drain regions (48) of p-channel transistor (50) counterdopes n type second level polysilicon to form p type polysilicon resistor (56) without effecting capacitor plates (36, 26) or the n type resistors (32, 34).

Method for forming a two-layered polysilicon gate electrode in a semiconductor device using grain boundaries

Abstract: A method is disclosed for forming a gate electrode having two polysilicon layers and a tungsten silicide layer to prevent fluorine gas diffusion along grain boundaries from penetrating into a gate oxide film This method for forming a gate electrode is comprised of sequentially forming a gate oxide film and a first polysilicon layer on a silicon substrate, enlarging the grain size of the first polysilicon layer by heat treatment, introducing a reagent gas, either SiH4 or Si2 H6, to further adjust the grain size within said layer, forming a second polysilicon layer on the first polysilicon layer, enlarging the grain size of the second polysilicon layer by heat treatment, introducing a reagent gas, either Si2 H6 or SiH4, whichever one was not used to treat the first polysilicon layer, forming a tungsten silicide layer on the second polysilicon layer, and patterning the tungsten silicide layer, the second polysilicon layer and the first polysilicon layer by means of a mask etching process

Integrated circuit structure having floating electrode with discontinuous phase of metal silicide formed on a surface thereof and process for making same

Abstract: A process is disclosed for forming an integrated circuit device, such as an EPROM device, with a floating gate electrode with a discontinuous phase of metal silicide formed on a surface thereof is described. The process for forming such a discontinuous phase of metal silicide on the surface of a polysilicon floating gate electrode for the device comprises the steps of depositing a first polysilicon layer over a substrate, and preferably over a thin oxide layer on the substrate capable of functioning as a gate oxide; then forming a very thin layer of a silicide-forming metal over the polysilicon layer; and heating the structure sufficiently to cause all of the silicide-forming metal to react with the underlying polysilicon layer to form metal silicide and to coalesce the metal silicide into a discontinuous phase on the surface of the polysilicon layer. When an EPROM device is to be constructed, the process includes the further steps of forming an first insulation layer over the structure; forming a second polysilicon layer over the first insulation layer; and then forming a second insulation layer over the second polysilicon layer. The structure is then patterned to form a dual gate electrode structure with a floating gate and a control gate. After doping of the underlying substrate to form the source and drain regions, a further oxide layer may be formed over the entire structure and contact openings may be cut to the source and drain regions and control gate electrode, thus completing formation of an EPROM device with a floating gate having a discontinuous phase of metal silicide on a surface thereof facing the control gate.

Method for forming a mesa-isolated SOI transistor having a split-process polysilicon gate

Abstract: A method for forming a mesa-isolated SOI transistor using a split-process polysilicon gate including the steps of depositing a layer of buried oxide (14) on a silicon substrate (12), depositing an SOI layer (16) on buried oxide layer (14), and forming a gate oxide layer (18) on the SOI layer (16). Further steps are to form a gate polysilicon mesa (20) on the gate oxide layer, and an SOI mesa (28) on gate polysilicon mesa (20) and forming an oxide sidewall (26) on the gate polysilicon mesa (20) and SOI mesa (28). A gate electrode (38) is the formed along with an oxide sidewall (36). Implanting gate electrode (38) with a boron implant occurs next, after which an oxide sidewall is formed on the gate electrode (38). The gate electrode (38) is implanted with phosphorus to form source and drain region. Thereafter annealing the structure takes place.

An analytic polysilicon depletion effect model for MOSFETs

Abstract: A novel polysilicon depletion model for MOSFET devices is presented. It is shown that only simple modifications to standard analytical MOSFET models used for circuit simulations are required to account for the polysilicon depletion effect. The accuracy of the model is validated by comparing results to both simulated and measured device characteristics. It is also shown that neglecting the polysilicon depletion effect for devices with nondegenerate polysilicon gates may lead to nonphysical model parameter values and large errors in the calculated intrinsic device capacitances. >

Method of making flash EEPROM memory cell

Abstract: A new method of obtaining an improved coupling ratio and short channel effect in a Flash EEPROM memory cell is shown. A trench is etched into a semiconductor substrate. A thick gate oxide layer is formed over the surface of the substrate and within the trench. A layer of silicon nitride is deposited and anisotropically etched away to leave spacers on the sidewalls of the trench. The spacers are overetched to expose an upper portion of the gate oxide layer on the trench sidewalls. The gate oxide layer not covered by the spacers is removed, exposing the horizontal silicon surface of the substrate in the bottom of the trench and the upper portion of the silicon sidewalls of the trench above the spacers. A tunnel oxide layer is grown on the exposed silicon surfaces of the substrate and within the trench wherein the controllable small area of tunnel oxide within the trench provides an improved coupling ratio and the long channel afforded by the trenched channel region improves the short channel effect of the memory cell. The silicon nitride spacers are removed. A first polysilicon layer is deposited within the trench. An interpoly dielectric layer is deposited over the first polysilicon layer followed by a second polysilicon layer. The layers are patterned to form a stacked polysilicon structure wherein the first polysilicon layer forms a floating gate and the second polysilicon layer forms a control gate. Source and drain regions are formed on either side of the stacked polysilicon structure.

Method of making LDD with polysilicon and dielectric spacers

Abstract: An improved FET device in which the hot carrier immunity and current driving capability are improved, and the subthreshold leakage current is minimized. The device has a gate electrode with vertical sidewalls, and a thin layer of SiO 2 over the electrode. A first polysilicon spacer is provided on the vertical sidewalls, with a second overlying oxide spacer over the first spacer. The top portion of the SiO 2 layer between the gate electrode and the polysilicon spacer is made conductive enough to keep the gate electrode and the polysilicon spacer at the same potential. Lightly doped source and drain regions are provided.

Method to ensure isolation between source-drain and gate electrode using self aligned silicidation

Abstract: A method for fabricating MOSFET devices with shallow source and drain diffusions, and high yielding self aligned refractory metal silicides was accomplished. This method involves forming a source and drain polysilicon diffusion layer, opening an hole in the polysilicon for the gate region, and fabricating oxide sidewalls in the hole to isolate the source and drain from a polysilicon gate. A polysilicon gate is than formed with a shape that will not allow the sides of this gate to experience subsequent metal deposition. A low temperature silicidation process than results in an absence of source and drain to gate polysilicon shorting or bridging, due to this unique gate polysilicon shape.

Performance and off-state current mechanisms of low-temperature processed polysilicon thin-film transistors with liquid phase deposited SiO/sub 2/ gate insulator

Abstract: Polysilicon thin-film transistors (poly-Si TFT's) with liquid phase deposition (LPD) silicon dioxide (SiO/sub 2/) gate insulator were realized by low-temperature processes ( >

Impact of polysilicon dry etching on 0.5 /spl mu/m NMOS transistor performance: the presence of both plasma bombardment damage and plasma charging damage

Abstract: Two types of damage mechanisms resulting from polysilicon gate dry etching are identified in 0.5 /spl mu/m NMOS transistors. One type of damage is found to be active even after full processing and to result in positive charge at the edge of the gate oxide. It is found to have no correlation with polysilicon antenna ratio and to be attributable to direct plasma bombardment. The other type of damage is found to be passivated after full processing but it is activated by electrical stress. After activation, this damage is an increasing function of polysilicon antenna ratio as well as overetch percentage. This second type of damage is attributable to plasma charging. >

Nitride cap sidewell oxide protection from BOE etch

Abstract: A new method of forming a self-aligned contact is achieved. A pattern of polysilicon gate electrode stack including a silicon oxide gate dielectric, a polysilicon gate electrode, a first thermal polyoxide layer over the top of said polysilicon gate electrode layer, a first silicon nitride layer over said first thermal polyoxide layer, and a TEOS layer over said silicon nitride layer is provided on a silicon substrate. Each of the layers has its side open to the ambient. Inert ions are implanted into the substrate which is not covered by the polysilicon gate electrode stack in such a manner as to reduce the possibility of the oxidation of the surface of the substrate. The pattern of polysilicon gate electrode stack and the surface of the said substrate are subjected to a thermal oxidizing ambient which causes oxidation of the sides open to the ambient of the polysilicon layer to form a second polyoxide layer on the sides of the polysilicon layer. A second silicon nitride layer is formed over the pattern of stack and the surface of the substrate. The second silicon nitride layer is anisotropically etched to remove the second silicon nitride from the top of the stack and from over the surface of the substrate while leaving the second silicon nitride layer remaining upon the sides of the stack to form a self-aligned opening to regions within the silicon substrate. A self-aligning contact to the regions is formed through said opening.

Advanced silicon and semiconducting silicon-alloy based materials and devices

Abstract: Preface Introduction (J F Nijs). Single Crystalline Silicon and its Alloys: Heavy doping effects in Silicon (P/Van Mieghem and R P Mertens): Introduction The physics of heavy doping effects Brief review of heavy doping effects Theories and models Influence of HDE on Silicon devices Summary References. Defects in crystalline silicon (C Claeys and J Vanhellemont): Introduction Structure of lattice defects Electronic properties of defects Device processing related defects Metallic contamination and gettering Impact on device properties References.Molecular beam epitaxy of silicon, silicon alloys and metals (E Kasper and C M Falco: introduction Electron beam evaporators and metals MBE Silicon Molecular beam epitaxy (Si-MBE) Applications of Silicon MBE References. Low thermal budget chemical vapour deposition techniques for Si and SiGe (M R Caymax and W Y Leong): Introduction Prerequisites for low-temperature growth Growth systems Kinetics of CVD growth of Si and SiGe in SiH^O 4/GeH^O4 systems Doping of low temperature Si and Si^O1-xGe^Ox layers Selective epitaxial growth (SEG) of Si and SiGe ^IIn-situ and ^Iex-situ characterisation References. Materials properties of (strained) SiGe layers (J Poortmans, S C Jain, J Nijs and R Van Overstraeten): Introduction: Structure and stability The Si-strained SiGe band alignments The indirect bandgap of strained Si^O1-xGe^Ox Transport properties and effective density of states in strained Si^O1-xGe^Ox layers References. SiGe heterojunction bipolar applications (J Poortmans, S C Jain and J Nijs): Introduction DC-behaviour of the double heterojunction bipolar transistor Frequency and circuit performance of HBT's with strained Si^O1-xGe^Ox-base Incorporation of strained Si^O1-xGe^Ox-layers in advanced bipolar technologies Conclusions References. Field-effect transistors, infrared detectors, and resonant tunneling devices in silicon/silicon-germanium and ^D*d-doped silicon (M Willander): Introduction Field-effect transistors Infrared detectors Resonant tunneling devices Summary References. Crystalline silicon-carbide and its applications (T Sugii): Introduction Physical properties Crystalline SiC growth Device application Summary References. Part Two: Polycrystalline silicon. Large grain polysilicon substrates for solar cells (S Martinuzzi and S Pizzini) Introduction Growth of polycrystalline (multicrystalline) silicon The role of oxygen, carbon and point defects in polycrystalline silicon Electrical properties of multicrystalline silicon wafers Conclusion References. Properties analysis and modelling of polysilicon TFTs (P Migliorato and M Quinn): Introduction Structural properties and density of states Effect of the DOS on the I-V characteristis Current-voltage characteristics Capacitance voltage characteristics Electric field at the drain and "kink" effect Conclusions Appendix References. Application and technology of polysilicon thin film transistors for liquid crystal displays (C Baert) Introduction Application of polysilicon thin film transistors Technology of polysilicon thin films Polysilicon TFT device structure Summary References. The use of polycrystalline silicon and its alloys in VLSI applications (M Y Ghannam): Introduction Deposition and structural properties of polysilicon Technological properties of LPCVD polysilicon films Electrical properties of polysilicon VLSI applications of polysilicon Other applications of polysilicon Semi-insulating polycrystalline silicon (SIPOS) Polycrystalline silicon/germanium alloys Biographical details. Keyword index.

High performance low temperature polysilicon thin film transistor using ECR plasma thermal oxide as gate insulator

Abstract: Electron cyclotron resonance (ECR) plasma thermal oxide has been investigated as a gate insulator for low temperature (/spl les/600/spl deg/C) polysilicon thin-film transistors based on solid phase crystallization (SPC) method. The ECR plasma thermal oxide films grown on a polysilicon film has a relatively smooth interface with the polysilicon film when compared with the conventional thermal oxide and it shows good electrical characteristics. The fabricated poly-Si TFT's without plasma hydrogenation exhibit field-effect mobilities of 80 (60) cm/sup 2//V/spl middot/s for n-channel and 69 (48) cm/sup 2//V/spl middot/s for p-channel respectively when using Si/sub 2/H/sub 6/(SiH/sub 4/) source gas for the deposition of active poly-Si films. >

Method for manufacturing offset polysilicon thin-film transistor

Abstract: In a method for fabricating an offset polysilicon thin-film transistor through the formation of silicide, the width of offset regions can be controlled as a narrow width of below 1 μm. Drain voltage is decreased due to the reduction of the offset regions' width. The effect of an increased parallel resistance and a bias voltage dependency of an overlap capacitance due to the arrangement of low concentration ion region reduces leakage current and improves the response to applied voltages. Also, gate voltage is decreased due to the decreased gate resistance when the polysilicon of the gate is substituted with the silicide.

Capacitor for a semiconductor device

Abstract: A semiconductor device having a capacitor of a large capacitance in spite of its small area, is composed of a first insulating film formed on a semiconductor substrate, a first polysilicon film, a second insulating film and a second polysilicon film which are formed in that order on the first insulating film. The second polysilicon film is connected to the semiconductor substrate by means of a metal film to function as one electrode while the first polysilicon film functions as the other electrode. The first and second insulating film are each made of a dielectric material.

LDD type MOS transistor

Abstract: A gate electrode comprises a N+ type polysilicon film and N- type polysilicon films directly contacted with side of the N+ type polysilicon film. Under the N+ type polysilicon films, N- type source.drain regions are provided in a P type silicon substrate to be coplanar with the main surface thereof.

The benefits of fluorine in pnp polysilicon emitter bipolar transistors

Abstract: BF/sub 2/ implantation into polysilicon and its subsequent rapid thermal diffusion into single crystal silicon is commonly used for the fabrication of pnp polysilicon emitter bipolar transistors. In this paper the effect of the fluorine, which is introduced into the polysilicon during the BF/sub 2/ implant, is investigated. Pnp polysilicon emitter bipolar transistors are fabricated in which the boron and fluorine are implanted separately, with the fluorine only going into one half of each wafer. Electrical results show that fluorine has two interrelated effects. In devices given a low thermal budget emitter drive-in, a drop in base current by a factor of approximately 3.2 is observed when the fluorine is present, together with an improvement in the ideality of the base characteristics. This is explained by the passivation of trapping states at the polysilicon/silicon interface by the fluorine. In contrast, in devices-given a higher thermal budget emitter drive-in, an increase in base current by a factor of approximately 2.5 is observed, when fluorine is present. This is explained by the action of the fluorine in accelerating the breakup of the interfacial layer. A model is proposed to explain this behavior. >

Control and modification of dopant distribution and activation in polysilicon

Abstract: Dopant distribution and activation in polysilicon is controlled by implanting electrically neutral atomic species which accumulate along polysilicon grain boundaries. Exemplary atomic species include noble gases and Group IV elements other than silicon.

Lightly doped drain transistor device having the polysilicon sidewall spacers

Abstract: A lightly doped drain (LDD) transistor device structure and a method of fabricating same are described. A silicon substrate is provided which has a trench formed therein. Polysilicon sidewall spacers are formed on the side walls of the trench. Silicon dioxide sidewall spacers are formed on the side walls of the polysilicon sidewall spacers. A gate oxide layer is formed on the bottom of the trench by oxidation. A polysilicon gate layer is formed filling the trench. Impurities are implanted into the silicon substrate to simultaneously form heavily doped source/drain areas in spaced apart portions of the silicon substrate adjacent to the polysilicon sidewall spacers to improve the conductivity of the polysilicon gate layer, and form lightly doped source/drain areas in spaced apart portions of the silicon substrate under the silicon dioxide sidewall spacers.

Semiconductor device having polysilicon resistors with a specific resistance ratio resistant to manufacturing processes

Abstract: A semiconductor device is disclosed that can effectively prevent a change in the resistance ratio of polysilicon resistor films when a plasma nitride film is formed above a plurality of polysilicon resistor films. The semiconductor device has metal interconnection layers 5a and 5b formed above polysilicon resistor films 3a and 3b, respectively. The ratio of the overlapping area of the polysilicon resistor film 3a and the metal interconnection layer 5a is set to be substantially equal to that of the polysilicon resistor film 3b and the metal interconnection layer 5b.

Method for manufacturing a conductor layer in a semiconductor device

Abstract: A method for manufacturing a conductor layer in a semiconductor device is achieved with a reduced resistivity in the conductor layer. When a polycide film comprised of a polysilicon film and a tungsten silicide film is manufactured, the grain size of the polysilicon film is increased to reduce the resistivity of the polysilicon film. Also, the silicon in the tungsten silicide film is transferred to the boundary between the tungsten silicide film and the polysilicon film to increase the adhesion properties therebetween. Accordingly, a lifting or separation phenomenon is eliminated. Furthermore, since the silicon in the tungsten silicide film is decreased by the transfer, the resistance of the conductor layer is reduced.

Method of fabricating lightly doped drain transistor device

Abstract: A lightly doped drain (LDD) transistor device structure and a method of fabricating same are described. A silicon substrate is provided which has a trench formed therein. Polysilicon sidewall spacers are formed on the side walls of the trench. Silicon dioxide sidewall spacers are formed on the side walls of the polysilicon sidewall spacers. A gate oxide layer is formed on the bottom of the trench by oxidation. A polysilicon gate layer is formed filling the trench. Impurities are implanted into the silicon substrate to simultaneously form heavily doped source/drain areas in spaced apart portions of the silicon substrate adjacent to the polysilicon sidewall spacers, improve the conductivity of the polysilicon gate layer, and form lightly doped source/drain areas in spaced apart portions of the silicon substrate under the silicon dioxide sidewall spacers.

Method of forming improved contacts from polysilicon to silicon or other polysilicon layers

Abstract: The method of the present invention introduces a method of forming conductively doped contacts on a supporting substrate in a semiconductor device that minimizes the lateral out-diffusion of the conductive dopants and also provides for a low resistive contact by the steps of: preparing a conductive area to accept contact formation; forming a phosphorus insitu doped polysilicon layer over the conductive area; forming an arsenic insitu doped polysilicon layer over the phosphorus insitu doped polysilicon layer, wherein the two insitu doped polysilicon layers are deposited one after another in separate deposition steps; and annealing the layers at a temperature range of approximately 900°-1100° C. thereby, resulting in sufficient thermal treatment to allow phosphorus atoms to break up a first interfacial silicon dioxide layer formed between the conductive area and the phosphorus insitu doped polysilicon layer.

Process for fabricating two loads having different resistance levels in a common layer of polysilicon

Abstract: The present invention provides a method of forming a first load having a first resistance level and a second load having a second resistance level in a common layer of polysilicon. In accordance with the method, a layer of polysilicon having a first resistance level is formed on a semiconductor circuit structure. A mask is then formed on the polysilicon layer to define areas of the polysilicon to be implanted with a dopant. The dopant is then implanted into the defined areas of the polysilicon to modify these areas to have a second resistance level. Selected areas of the polysilicon layer are then etched away to form first load regions having the first resistance level and second load regions having the second resistance level.

Method for fabricating self-aligned polysilicon contacts on FET source/drain areas

Abstract: Improved N-channel and P-channel field effect transistor device structure having self-aligned polysilicon pads contacts and a process for making such devices has been achieved. The doped polysilicon pad contact are formed over the source/drain areas of the field effect transistors and are used to form shallow self-aligned diffused contact to the source/drain areas. These polysilicon pads provide a low resistance ohmic contacts that are free from implant damage that would otherwise cause increased junction leakage current and are free of metal spiking at the source/drain area perimeter that would cause metal contact to substrate shorts. The increased area of the polysilicon pads over the source/drain area allows for relaxed design ground rule for the contact openings, making for a more manufacturable process for Ultra Large Scale Integration applications.