Showing papers on "Programmable logic device published in 1994"

Logical devices implemented using quantum cellular automata

Abstract: We examine the possible implementation of logic devices using coupled quantum dot cells. Each quantum cell contains two electrons which interact Coulombically with neighboring cells. The charge distribution in each cell tends to align along one of two perpendicular axes, which allows the encoding of binary information using the state of the cell. The state of each cell is affected in a very nonlinear way by the states of its neighbors. A line of these cells can be used to transmit binary information. We use these cells to design inverters, programmable logic gates, dedicated AND and OR gates, and non‐interfering wire crossings. Complex arrays are simulated which implement the exclusive‐OR function and a single‐bit full adder.

A high-performance microarchitecture with hardware-programmable functional units

Abstract: This paper explores a novel way to incorporate hardware-programmable resources into a processor microarchitecture to improve the performance of general-purpose applications. Through a coupling of compile-time analysis routines and hardware synthesis tools, we automatically configure a given set of the hardware-programmable functional units (PFUs) and thus augment the base instruction set architecture so that it better meets the instruction set needs of each application. We refer to this new class of general-purpose computers as PRogrammable Instruction Set Computers (PRISC). Although similar in concept, the PRISC approach differs from dynamically programmable microcode because in PRISC we define entirely-new primitive datapath operations. In this paper, we concentrate on the microarchitectural design of the simplest form of PRISC—a RISC microprocessor with a single PFU that only evaluates combinational functions. We briefly discuss the operating system and the programming language compilation techniques that are needed to successfully build PRISC and, we present performance results from a proof-of-concept study. With the inclusion of a single 32-bit-wide PFU whose hardware cost is less than that of a 1 kilobyte SRAM, our study shows a 22% improvement in processor performance on the SPECint92 benchmarks.

Programmable application specific integrated circuit and logic cell therefor

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Field-Programmable Gate Array Technology

Abstract: Preface. 1: Introduction. 1.1. Logic Implementation Options. 1.2. What is an FPGA? 1.3. Advantages of FPGAs. 1.4. Disadvantages of FPGAs. 1.5. Technology Trends. 1.6. Designing for FPGAs. 1.7. Outline of Subsequent Chapters. 1.8. References. 2: SRAM Programmable FPGAs. 2.1. Introduction. 2.2. Programming Technology. 2.3. Device Architecture. 2.4. Software. 2.5. The Future. 2.6. Design Applications. 2.7. Acknowledgements 2.8. References. 3. Antifuse Programmed FPGAs. 3.1. Introduction. 3.2. Programming Technology. 3.3. Device Architecture. 3.4. Software. 3.5. The Future. 3.6. Design Applications. 3.7. Acknowledgements. 3.8. References. 4. Erasable Programmable Logic Devices. 4.1. Introduction. 4.2. Programming Technology. 4.3. Device Architecture. 4.4. Software. 4.5. The Future. 4.6. Design Applications. 4.7. References. Index.

Logic structure and circuit for fast carry

Abstract: Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things, for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The invention takes advantage of the fact that a carry signal to be added to two bits can be propagated to the next more significant bit when the two binary bits to be added are unequal, and that one of the bits can serve as the carry signal when the bits are equal. For each bit, a carry propagate signal is generated by a lookup table programmable function generator and is used by dedicated hardware to generate the carry signal.

Programmable logic device including a parallel input device for loading memory cells

Abstract: A device for configuring portions of an array of memory cells for a programmable logic device comprises a data register, a plurality of shift registers and a control unit. The data are loaded into and out of the data register in parallel. Each of the outputs of the data register is coupled to a serial input of a respective shift register so the data can be shifted into the shift registers at the same time. A clock signal is applied by the control unit to the shift registers for serially loading the plurality of shift registers in parallel. The clock signal and the load signal are preferably applied simultaneously until the plurality of shift registers store a column of data to be transferred to the memory cells. The plurality of shift registers each have a plurality of data outputs. Each of the data outputs is coupled to a different row of memory cells. The control unit then generates an address signal to transfer the column of data held in the plurality of shift registers into the memory cells.

Method for programming an FPLD using a library-based technology mapping algorithm

Abstract: A method for programming a programmable logic device (FPLD) to implement a circuit design using a library of elements made up of general logic functions and an invert function. The general logic functions represent groups of the 22.spsp.n specific logic functions which can be stored in an n-input lookup table addressing 2n data signals. The specific logic functions of each group differ by one or more inverted input signals and/or an inverted output signal. The method includes the step of technology mapping the circuit design using the library of elements. The general logic functions are assigned a finite value and the invert function is assigned a zero cost (or a very small cost). A subcircuit of the circuit design having n input signals (or less) and one output will always match one logic element from this library.

An FPGA for implementing asynchronous circuits

Abstract: Field-programmable gate arrays are a dominant implementation medium for digital circuits, especially for glue logic. Unfortunately, they do not support asynchronous circuits. This is a significant problem because many aspects of glue logic and communication interfaces involve asynchronous elements, or require the interconnection of synchronous components operating under independent clocks. We describe Montage, the first FPGA to explicitly support asynchronous circuit implementation, and its mapping software. Montage can be used to realize asynchronous interface circuits or to prototype complete asynchronous systems, thus bringing the benefits of rapid prototyping to asynchronous design. Unfortunately, implementation media for asynchronous circuits and systems have not kept up with those for the synchronous world. Programmable logic devices do not include the special non-digital circuits required by asynchronous design methodologies (e.g., arbiters and synchronizers) nor do they facilitate hazard-free logic implementations. This leads to huge inefficiencies in the implementation of asynchronous designs as circuits require a variety of seperate devices. This has caused most asynchronous designers to focus on custom or semi-custom integrated circuits, thus incurring greater expense in time and money. The net effect has been that optimized and robust asynchronous circuits have not become a part of typical system designs. The asynchronous circuits that must be included are usually designed in an ad-hoc manner with many underlying assumptions. This is a highly error- prone process, and causes implementations to be unnecessarily delicate to delay variations. Field-programmable gate arrays, one of today's dominant media for prototyping and implementing digital circuits, are also inappropriate for constructing more than the simplest asynchronous interfaces. They lack the critical elements at the heart of today's asynchronous designs. Unfortunately, resolving this problem is not just a simple matter of adding these elements to the programmable array. The FPGA must also have predictable routing delay and must not introduce hazards in either the logic or routing. Futhermore, the mapping tools must also be modified to handle asynchronous concerns, especially the proper decomposition of logic to fit into the programmable logic blocks and the proper routing of signals to ensure that required timing relationships are met. Ideally, we need an FPGA that can support both synchronous and asynchronous circuits with comparable efficiency. As a step in this direction we present Montage, an integrated system of FPGA architecture and mapping software designed to support both asynchronous circuits and synchronous interfaces. The architecture provides circuits with hazard-free logic and routing, mutual exclusion elements to handle metastability, and methods for initializing unclocked elements. The mapping software generates placement and signal routing sensitive to the timing demands of asynchronous methods. With these features, the Montage system forms a prototyping and implementation medium for asynchronous designs, providing asynchronous circuits with a powerful tool from the synchronous designer's toolbox.

Modeling programmable logic controllers for logic verification

Abstract: Verification method has been developed for determining the safety and operability of programmable logic controller (PLC) based systems. The method automatically checks sequential logic embedded in PLCs and provides counterexamples if it finds errors. The method consists of a system model, assertions, and a model checker. The model is a Boolean-based representation of a PLC's behavior. Assertions are questions about the behavior of the system, expressed in temporal logic. The model checker generates a state space based on the above two inputs, searches the space efficiently, determines the consistency of the model and assertions, and supplies counterexamples. A modeling technique has been developed to verify relay ladder logic (RLL), a PLC programming language. The performance of the model checker is studied in a series of alarm designs. >

Method for programming complex PLD having more than one function block type

Abstract: A method for programming programmable logic devices (PLDs) having multiple function block types to implement a logic function, whereby the logic function is mapped into one of the function block types before being mapped into the remaining function block types. In one embodiment, a PLD containing both "fast" function blocks (FFBs) and "high density" function blocks (HDFBs) are programmed such that the FFBs are programmed prior to the HDFBs. This method maximizes the overall speed of an implemented logic function.

Hierarchically connected reconfigurable logic assembly

Abstract: A plurality of electronically reconfigurable gate array (ERCGA) logic circuits are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected circuits. The reconfigurable interconnect permits the digital network realized on the interconnected circuits to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA circuits dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic circuits. Other reconfigurable interconnect topologies are also detailed. If desired, the logic circuits and interconnect can be implemented in wafer-scale technology. Hybrid simulation employing both an ERCGA hardware simulator and a second simulator permits intermediate states of a circuit's operation to be reached quickly and analyzed in detail.

Macrocell with product-term cascade and improved flip flop utilization

Abstract: A programmable logic device having macrocells (53, 40, 55) enables gate cascades between macrocells (51, 56) to occur with a faster signal transit time, while preserving the flip flop function of the cascaded macrocells by reallocating a redirectable flip flop reset product term (42) to the flip flop (47) input. All gate product terms are retained during cascading. The macrocell logic is optimized for fast signal transit with selectable flip flop clocking. Multiplex clocking (64) and programming (CB1, CB2, CB3) are done with fewer transistors in the signal path, further reducing signal transit time.

Application specific modules in a programmable logic device

Abstract: A structure and a method provide a programmable logic device (200) including a number of generic logic blocks (203a-203l) or more application-specific block (203b). Such application-specific block implements a specific function, such as a register file or a memory array (420). In one embodiment, the application-specific block is programmable to be either one or more single-port memory array, a first-in-first-out (FIFO) memory, or a dual port memory array. In another embodiment, the application-specific block can be configured to be a register file, a number of counters, a number of timers, or a shift register. The application-specific block can be used in conjunction with programmable logic arrays for multiplexing input and output signals into and out of the application-specific block. Interconnectivity between the generic logic blocks and the application-specific blocks, using a global routing resource, integrates into a programmable logic device, functions otherwise difficult to implement using only generic logic blocks.

Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers

Abstract: A programmable logic device is provided that contains a plurality of logic array blocks arranged in rows and columns. The logic array blocks are interconnected with horizontal conductors in each row and vertical conductors in each column. The logic array blocks and the interconnections between conductors are configured using programmable logic. Some of the programmable logic is used to selectively connect logic array block input terminals to the horizontal conductors. Additional logic in each column is used to selectively connect the horizontal conductors to either logic array block output terminals from the same column or logic array block output terminals from an adjacent column. The additional logic prevents certain interconnection pathways from being blocked and increases the overall flexibility of the interconnection scheme of the programmable logic device, thereby improving device performance.

Field programmable gate array with built-in bitstream data expansion

Abstract: A programmable gate array comprises an array of configurable logic blocks. Each configurable logic block is controlled by one or more rows and columns of memory cells in a memory array. According to the invention, an older bitstream may be used without modification in a newer programmable gate array. A frame register includes a plurality of active memory locations called frame bits which correspond to columns of memory cells within the memory array and at least one spare frame bit which does not correspond to a column of memory cells within the memory array. A similar configuration of row pointer cells comprises a shift register for enabling row by row addressing of the memory array. Spare frame bits and spare pointer cells are selectively either loaded or bypassed by programmable selector circuits, permitting expansion of the memory array in future programmable gate arrays, and thereby allowing additional functionality to be added to later versions of the programmable gate array without requiring designers of gate array applications to modify bitstreams which they previously designed.

Field programmable logic device with dynamic interconnections to a dynamic logic core

Abstract: The architecture, operation and design of a novel Field Programmable Logic Device is described. The device (20) implements a circuit by using a dynamic logic core (22) that executes staged logic corresponding to the logic levels of the implemented circuit. Logic inputs to the dynamic logic core are obtained from a dynamic interconnection array (26). Appropriate logic inputs for a given logic level are dynamically selected and routed by the dynamic interconnection array (26). When necessary, the dynamic interconnection array (26) buffers signals which are required at subsequent logic levels. The dynamic interconnection array (26) selects logic inputs for a given logic level from circuit input signals, buffered signals and dynamic logic core output signals.

Programmable logic array with local and global conductors

Abstract: A programmable logic array integrated circuit has a plurality of programmable logic elements grouped into a plurality of mutually exclusive groups Each group includes signal conductors uniquely associated with that group for conveying signals between the programmable logic elements in that group Other signal conductors are provided for conveying signals between the groups Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors

Integrated circuit facilitating simultaneous programming of multiple antifuses

Abstract: To facilitate the simultaneous programming of multiple antifuses on an integrated circuit, a first current path is established from a first programming terminal (VPP1) of a programmable logic device through a first antifuse to be programmed and a second current path is established from a second programming terminal (VPP2) of the programmable logic device through a second antifuse to be programmed. By supplying the programming current for programming the first antifuse from a different terminal than the programming current for programming the second antifuse, the two antifuses can be programmed simultaneously with an adequate amount of programming current being supplied to each antifuse. A programming current multiplexer circuit is disclosed for selectively coupling either a first programming voltage (VPP1) terminal, a second programming voltage (VPP2), or a ground terminal (GND) to a programming bus and/or to an antifuse to be programmed. The first and second current paths can be established using multiple such programming current multiplexer circuits.

Estimation of circuit activity considering signal correlations and simultaneous switching

Abstract: This paper presents accurate estimation of signal activity at the internal nodes of CMOS combinational logic circuits. The methodology is based on stochastic model of logic signals and takes correlations and simultaneous switching of signals at logic gate inputs into consideration. In combinational logic synthesis, in order to minimize spurious transitions due to finite propagation delays, it is crucial to balance all signal paths and to reduce the logic depth. As a result of balancing delays through different paths, the inputs to logic gates may switch at approximately the same time. We have developed and implemented an technique to calculate signal probability and switching activity of the CMOS combinational logic circuits. Experimental results show that if simultaneous switching is not considered the switching activities of the internal nodes can be off by more than 100% compared to simulation based techniques. In contrast, our technique is on the average within 2% of logic simulation results.

Mask-programmed integrated circuits having timing and logic compatibility to user-configured logic arrays

Abstract: Method and apparatus for producing mask-configured integrated circuits which are pin, logic, and timing compatible substitutes for user-configured logic arrays (10), without the need for logic or timing simulations of the mask-configured circuit design. Scan testing networks of test blocks and modified flip-flops are included in the mask-configured substitutes to test functionality. Logic compatibility to the user-configured logic array (an FPGA) (10) is preserved by clustering together in the mask-configured integrated circuit (a gate array) (16) all of the logic gates which perform the functions of a particular FPGA logic block. Moreover, only those FPGA logic gates or functions which are used are replicated in the gate array, to conserve chip area.

Apparatus and method for automatic test generation and fault simulation of electronic circuits, based on programmable logic circuits

Abstract: An electronic circuit test vector generation and fault simulation apparatus is constructed with programmable logic devices (PLD) or field programmable gate array (FPGA) devices and messaging buses carrying data and function calls. A test generation and fault simulation (TGFS) comparator is implemented in the PLD or FPGA consisting of a partitioned sub-circuit configuration, and a multiplicity of copies of the same configuration each with a single and different fault introduced in it. The method for test vector generation involves determining test vectors that flag each of the fault as determined by a comparison of the outputs of the good and single fault configurations. Further the method handles both combinational as well as sequential type circuits which require generating a multiplicity of test vectors for each fault. The successful test vectors are now propagated to the inputs and outputs of the electronic circuit, through driver and receiver sub-circuits, modeled via their corresponding TGFS comparators, by means of an input/output/function messaging buses. A method of fault simulation utilizing the TGFS comparators working under a fault specific approach determines the fault coverage of the test vectors.

Multiplexed control pins for in-system programming and boundary scan testing using state machines in a high density programmable logic device

Abstract: A structure and a method to implement in-system programming (ISP) and boundary-scan testing in an integrated circuit using the same pins to control both functions. The SDI, SCLK, MODE and SDO connections required for in-system programming and the TDI, TCK, TMS and TDO connections required for boundary-scan testing are multiplexed such that they are provided from the same four pins. An in-system programming enable pin is used to control the multiplexing of these pins. In an alternative embodiment, both in-system programming and boundary-scan testing are performed using the same pins and the same state machine. The test logic architecture specified in IEEE Standard 1149.1-1990 is utilized. To implement the in-system programming instructions, the instruction register of Std. 1149.1-1990 is modified to include private instructions which perform the desired programming functions.

A case study on hardware/software partitioning

Abstract: We present an analysis of a fully automatic method to accelerate standard software in C or C++ by use of field programmable gate arrays. Traditional compiler techniques are applied to the hardware/software partitioning problem and a compiler is linked to state of the art hardware synthesis tools. Time critical regions are identified by means of profiling and are automatically implemented in user programmable logic with high level and logic synthesis design tools. The underlying architecture is an add-on board with user programmable logic connected to a Spare based workstation via the system bus. We present an analysis and case study of this method. Eight programs are used as test cases and the data collected by applying this method to programs is used to discuss potentials and limitations of this and similar methods. We discuss architectural parameters, programming language properties, and analysis techniques. >

Maintenance monitor system

Abstract: The system is provided for controllably monitoring data associated with operational characteristics of an engine. The system determines a maintenance activity requirement based on such characteristics. The system includes a plurality of transducers associated with the engine and connected to a programmable logic device. Signals from the transducers are continuously monitored and stored in an associated storage device. In response to predetermined sets of operational characteristics, an indication of when maintenance is due on the engine is produced by the logic device.

Logic synthesis for field-programmable gate arrays

Abstract: In this paper, we consider the problem of configuring Field Programmable Gate Arrays (FPGA's) so that some given function is computed by the device. Obtaining the information necessary to configure a FPGA entails both logic synthesis and logic embedding. Due to the very constrained nature of the embedding process, this problem differs from traditional multilevel logic synthesis in that the structure (or lack thereof) of the synthesized logic is much more important. Furthermore, a metric-like literal count is much less important. We present a communication complexity-based decomposition technique that appears to be more suitable for FPGA synthesis than other multilevel logic synthesis methods. The key is that our logic optimization technique based on reducing communication complexity is good enough to allow a simple technology mapping to work well for FPGA devices. >

The future of programmable logic and its impact on digital system design

Abstract: Field programmable gate arrays (FPGAs) combine the high-integration benefits of gate arrays with the time-to-market benefits of a user-programmable device. Already a mainstream logic technology, the growth rate of FPGA usage will continue to exceed that of other ASIC technologies. FPGA technology is having a major impact on electronic system design, especially through the use of FPGAs as reconfigurable computing elements. >

Programmable logic device having fast programmable logic array blocks and a central global interconnect array

Abstract: A programmable logic device has a number of dedicated global control input lines which interface directly with individual building blocks known as logic array blocks. These lines can be used for clocks, presets, clears, or output-enables. Other logic signal lines from the centrally located global interconnect array are selected through an array of multiplexers and then interface with the logic array block. A configuration array of multiplexers in the logic array block selects from among these inputs, generating local control input signals, the final functions of which are decided by further multiplexing at the macrocell level within the logic array block.

Data recording and display system

Abstract: A system is disclosed for sensing, recording, and selectively displaying data associated with operational characteristics of a vehicle and associated engine. The system includes a plurality of transducers delivering signals corresponding to such operational characteristics to a programmable logic device. These signals are converted to appropriate information signals which are stored in an associated storage device and can be selectively displayed on a suitable display device.

An Optoelectronic 3-D Field Programmable Gate Array

Abstract: Traditional Field-Programmable Gate Arrays suffer from a lack of routing resources when implementing complex logic designs. This paper proposes two possible improvements to the FPGA structure that could alleviate these problems. We suggest extending the FPGA class to 3-D architectures. The 3-D architectures could be constructed of a stack of optically interconnected 2-D planes. Furthermore, we suggest a hierarchical distribution of routing resources that closely matches the wire length distributions of the intended class of applications.

Circuit for fast carry and logic

Abstract: Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function. When a large number of bits is to be processed, the carry function typically causes significant delay or requires significant additional components to achieve a result at high speed. The present invention provides dedicated hardware within the logic blocks for performing the carry function quickly and with a minimum number of components. The circuit includes additional structures to allow the fast carry hardware to perform additional commonly used functions.