Showing papers on "RC circuit published in 1991"

On the representation of infinite-length distributed RC one-ports

Abstract: Representations of infinite distributed RC one-ports are described. Two functions are introduced: the dipole intensity function (as the generalization of pole-zero pattern) and the time-constant density (as the generalization of the discrete time-constant set of a lumped network). Relations between these representations and the complex impedance are presented. These representations can be regarded as the generalization of the descriptions commonly used in the theory of lumped networks. The representations offer possibilities for the identification and for the synthesis of distributed RC networks. Although the representations were introduced for the case of RC networks, the results can also be applied directly for inductance-resistance networks. The use of the new representations is demonstrated by some examples. >

Electrostatic discharge detection and clamp control circuit

Abstract: A switching element is connected to an integrated circuit for shunting an ESD pulse away from the integrated circuit features. A plurality of detection circuits responsive to typical ESD waveform characteristics provide logical control of the switching means. In the preferred embodiment, a NAND gate drives the switching element. The first input to the NAND gate is a first RC network having a first time constant that exceeds the characteristic rise time of the typical ESD pulse, but not the characteristic duration of the typical ESD pulse. The second input to the NAND gate is a feedback loop from the NAND gate output. The feedback loop includes a second RC network having a second time constant that exceeds the duration of a noise pulse, a third RC network having a third time constant that approximates the characteristic duration of the typical ESD pulse, and an inverter between the second and third RC networks. Application of the ESD pulse causes the first input to drive the NAND gate, thus turning on the switching element, and if the ESD pulse is still present when the second time constant is exceeded, the switching means is latched on via the second input until the third time constant is exceeded.

Low harmonic compact fluorescent lamp ballast

Abstract: A high frequency electronic ballast for a lamp (20) includes an LC filter (5) and a voltage doubler circuit (8) coupling AC input terminals (1, 2) to DC input terminals (13, 14) of a half bridge DC/AC converter circuit (15). One end of the lamp is coupled to the capacitors (16, 17) of the voltage doubler circuit via a coupling capacitor (21) and the voltage doubler diodes (11, 12) and the other end of the lamp is coupled via an LC circuit (24, 25 and 26) to a junction point (22) between first and second switching transistors (18, 19) of the half bridge circuit. A capacitor including the lamp and the LC circuit so that the half bridge circuit will oscillate at a high frequency. Energy is fed back to the voltage doubler capacitors via the coupling capacitor and the LC circuit to maintain the capacitor voltage above the peak of the AC supply voltage and thereby provide a circuit with a high power factor and low harmonic line current.

Semiconductor device containing voltage converting circuit and operating method thereof

Abstract: The semiconductor memory device contains a voltage converting circuit. The voltage converting circuit includes a plurality of reference voltage generating circuits for respectively generating a plurality of reference voltages at different levels. The voltage converting circuit further includes a differential amplifier, an output circuit, a switching circuit and a switching control circuit. The switching control circuit and the switching circuit select one of the plurality of reference voltages and supply the selected reference voltage to the differential amplifier in response to an externally applied control signal. The differential amplifier and the output circuit apply the supplied reference voltage to an internal circuit.

Device and method for programming critical hardware parameters

Abstract: A control register residing in a circuit chip stores a set of hardware parameters which exercise programmable control over circuits in the chip to allow for various critical hardware options. A plurality of chips and their control registers may be addressed and written individually by a processor through normal bus access. Each control register is permitted to be written only once, shortly after reset. A circuit, in response to a reset signal and a chip select signal, enables the individual control register for writing, and further, in response to a write strobe, latches data from the data bus into the register and soon afterwards ceases enabling the register for further writes. The various hardware options responsive to the hardware parameters include allowing for various bus interfaces, trimming the time constant of an analog RC circuit which provides internal bus timing strobes, switching internal timing strobes to external pads for output, switching external timing strobes from external pads to replace the internal strobes, and floating the outputs of all output pad drivers for junction leakage tests.

Evaluating RC-interconnect using moment-matching approximations

Abstract: The authors describes a relation for specifying the 'optimal' number of lumped RC sections needed to approximate a distributed RC element for an estimated digital-signal bandwidth. The bandwidth approximation also aids in determining the order of the AWE (asymptotic waveform evaluation) approximation for the driving-point and transfer function models. Since moving to arbitrarily high orders of approximation to meet the bandwidth requirements is complicated by moment-matching instability problems, a constrained mapping from moments to dominant time constants is used which guarantees stability for RC interconnect models. >

Temperature detection circuit used in thermal shielding circuit

Abstract: A temperature detection circuit includes first and second current sources and a comparing circuit. A first current source generates a current having a positive temperature coefficient and flowing in a band gap type voltage source. A second current source generates a current having a zero or negative temperature coefficient. The comparing circuit compares the amounts of currents flowing in the first and second current sources to detect the relation between the magnitudes of the compared currents.

CMOS output driver with transition time control circuit

Abstract: A single resistance permits a CMOS driver to have output devices that controllably transition "fast off-slow on" and which are not simultaneously on while the driver switches states The driver's output and supply currents contain reduced harmonics The resistance is coupled to the gates of the output stage PMOS-NMOS devices, and forms an RC circuit with the intrinsic capacitance at the gates, extending the turn-on transition of the gate drive voltages Each output device then turns on relatively slowly, but turns off normally The output current transition times are essentially determined by the resistance and intrinsic capacitances The resistance is implemented using polysilicon or diffusion, and preferably has a magnitude ten times the on-channel resistance of the input PMOS and NMOS devices driving the output stage Because the resistance and intrinsic capacitances are essentially temperature and power supply voltage independent, and but slightly process dependent, the current output transition times can be controlled despite CMOS parameter variations A 3-state embodiment of the CMOS buffer uses parallel coupled PMOS-NMOS devices to switchably couple in the resistance between both output gates when the enable signal is high Second input PMOS and NMOS devices, connected in parallel across the first input PMOS and NMOS devices, turn on across the first input devices when the enable signal is low A high enable signal enables the driver circuit, while a low enable signal uncouples the resistance and turns off both output PMOS and NMOS devices, putting the circuit's output in a high impedance state

Power-on reset architecture

Abstract: A power-on reset circuit for providing a reset signal to an active device on an integrated circuit (IC). The circuit includes a RC circuit for producing a reset signal until its capacitor fully charges. The circuit also includes a voltage detector for preventing the charge from collecting on the capacitor of the RC circuit until the voltage is at a functional level.

Improved small-signal equivalent circuit model and large-signal state equations for the MOSFET/MODFET wave equation

Abstract: A simple non-quasi-static small-signal equivalent circuit model is derived for the ideal MOSFET wave equation under the gradual channel approximation. This equivalent circuit represents each Y-parameter by its DC small-signal value shunted by a (trans) capacitor in series with a charging (trans) resistor. A large-signal model for the intrinsic MOSFET is derived by first implementing this RC topology in the time domain. Modified state equations are then introduced to enforce charge conservation. Transient simulations with this approximate large-signal model yield results that are compared with reported exact numerical analysis for the long channel MOSFET for a wide range of bias conditions. This unified small- and large-signal model applies to both the three- and four-terminal intrinsic MOSFET in the region of the channel where the gradual channel approximation is applicable. A non-quasi-static small-signal equivalent circuit for the velocity-saturated MOSFET wave equation is also reported. >

Group delay as an estimate of delay in logic

Abstract: It is an accepted practice in signal delay estimation to model MOS digital circuits as RC circuits. In most cases Elmore's definition is exactly equivalent to the group delay of the network at zero frequency. A computationally efficient noniterative method to calculate this delay for networks with any linear elements and arbitrary topology is presented. It is shown that in RC networks under certain conditions, the Elmore delay and the 50% unit step response delay are related by a constant which is largely independent of the element values and topology. An efficient method to obtain sensitivities of the delay with respect to any element in the network is presented. >

Integrated circuit for generating a reset signal

Abstract: An integrated circuit for generating a reset signal includes terminals for a first and a second supply potential. A serial RC network is connected between the terminals. The RC network has an ohmic component, a capacitive component and a first circuit node of the integrated circuit connected between the components. An initializing circuit is connected parallel to the RC network. The initializing circuit has an output forming a second circuit node of the integrated circuit carrying a potential with a maximum value specified by dimensioning the initializing circuit, when the first supply potential is applied. An inverter circuit is connected between the first circuit node and the terminal for the second supply potential in terms of supply voltage. The inverter circuit has an input connected to the second circuit node and an output forming a third circuit node of the integrated circuit. A transistor has a source-to-drain path connected between the second circuit node and the terminal for the second supply potential and has a gate connected to the third circuit node. An additional inverter has an input at the third circuit node and an output forming a fourth circuit node of the integrated circuit at which a reset signal is present during operation.

Output buffer circuit for lsi circuit

Abstract: An output buffer circuit for an LSI circuit includes a control signal generating circuit, responsive to a signal at either one of first and second levels from an internal logic circuit for generating a control voltage at a level which is sufficient to reliably turn off the PMOSFET of a first CMOS circuit in the output buffer circuit. When the PMOSFET of the first CMOS circuit is turned off, a feedback circuit applies to the gate electrode of the PMOSFET, a signal at a level sufficient to maintain the PMOSFET in the non-conductive state regardless of changes in the control voltage while the signal from the internal logic circuit is at above-stated one level.

Transhybrid loss with RC balance circuits for primary-rate ISDN transmission systems

Abstract: The authors report a method for the reduction of the near-end echo in the subscriber loop environment for primary-rate ISDN full-duplex data transmission. The technique uses an RC network as the matching input line impedance at the transmitter to reduce the near-end echo. Data rates ranging from the ISDN basic rate with (2B+D) channels to primary rate with (23B+D) channels are covered. The results indicate that a single basic configuration for the balancing line impedance may be adapted to keep the transhybrid loss in the range of about 22 dB in the worst case over the entire frequency range of interest. The balancing procedure for the hybrid takes place in a training sequence during which the component values of the RC matching circuit are adjusted from their initial values by an iterative adaptation procedure. Two techniques for optimizing the component values have been verified. For all cases examined, including worst-case line configurations, the components of the RC matching circuit have converged to final values, for which the minimum transhybrid loss had a maximum above 20 dB. >

Waveform relaxation for linear RC-circuits

Abstract: Recent techniques for the convergence analysis of Picard-Lindelof iteration are applied to linear RC-circuits. A particular decomposition technique is presented which always leads to a convergent process.

A recursive technique for computing delays in series-parallel MOS transistor circuits

Abstract: An efficient recursive technique for computing the Elmore delay in series-parallel resistance-capacitance (RC) networks is presented. The time complexity of the algorithm is on the order of the number of resistors times the number of nodes to which the delay has to be computed. In this respect it is superior to other known methods, particularly to that of P.K. Chan Karplus. Although that algorithm is more general, the present method should be attractive given the fact that many VLSI MOS circuits are based on design styles which are restricted to series-parallel transistor networks, which, in particular, exclude bridges. A special type of series-parallel RC circuit occurs in interconnection networks driven by multiple sources. A variation on the first algorithm, which is especially useful in a hierarchical simulator, is presented for computing the Elmore delay in such networks. >

Electric circuit for providing a high tension impulse, particularly for a defibrillator

Abstract: The HV pulse circuit uses a series of capacitors (C1...Cn) connected in a series circuit via associated switches (S1...Sn) for selective discharge of the capacitors (C1...Cn). The latter are charged in a parallel circuit, with stored energy within the circuit used for operating the switches (S1...Sn). Pref. a control unit is used for controlled connection of the charged capacitors (C1...Cn) in the series circuit, to obtain a voltage pulse with a given signal characteristic.

Integrator and image read device

Abstract: An integrator having a first circuit including an integrating capacitor and a feedback resistor, both being connected in parallel to each other in a negative feedback loop of the first circuit, and a second circuit, connected to an output side of the first circuit, for compensating for a leak by the feedback resistor. The first circuit operates as an integrator in high frequencies, and as a current-voltage converter in low frequencies. Further, the second circuit compensates for the leak by the feedback resistor, thereby to produce a value indicative of the result of integrating an input current.

DARSI: RC data reduction (VLSI simulation)

Abstract: Taking into account RC effects in VLSI simulation and verification systems, without seriously degrading their efficiency, requires preliminary data reduction. A tool, DARSI (data reduction system for interconnects), that can handle both polysilicon and diffusion resistive effects is presented. It contains the reduction scheme described by S.-L. Su et al. (Proc. IEEE Conf. Computer-Aided Design, p.270-3, 1986), a novel line-based reduction method, a novel loop reduction scheme, and a technique for identifying important diffusion resistors. The number of parasitic elements is considerably reduced, while guaranteeing delay errors to be less than a few percent. DARSI is implemented in a general-purpose rule-based verification environment for VLSI and has a nearly linear complexity. Application to several practical designs is also discussed. >

Clocked driver circuit stabilized against changes due to fluctuations in r.c. time constant

Abstract: A clocked driver circuit includes a first gate circuit, a second gate circuit, a first time constant circuit, a second time constant circuit, a first switching circuit, and a second switching circuit. The first gate circuit has one input terminal connected to a first input terminal. The second gate circuit has one input terminal connected to a second input terminal. The first time constant circuit is connected between the output terminal of the first gate circuit and the other input terminal of the second gate circuit. The second time constant circuit is connected between the output terminal of the second gate circuit and the other input terminal of the first gate circuit. The first switching circuit controls the time constant of the first time constant circuit in accordance with an output from the first gate circuit. The second switching circuit controls the time constant of the second time constant circuit in accordance with an output from the second gate circuit.

A CMOS analog-digital integrated circuit for charged particle spectrum measurements

Abstract: The authors present a CMOS analog-digital integrated circuit implemented using metal oxide semiconductor implementation system (MOSIS) fabrication to be used for nuclear radiation measurements. They have implemented a charge sensitive preamplifier, operational amplifiers, RC filters, a peak detector, low-voltage comparators, a low-voltage analog switch, logic and control circuits, flip-flops, and counter cells. On the system level they have built an analog-digital block, suitable for charged particle spectrum measurements, using an external solid-state detector. The particle energy spectrum is measured in 10 channels and stored in equinumber 11-b registers, which can then be selectively addressed, read out, and reset. The overall noise performance with no detector connected is equivalent to 10-keV proton energy. The whole system can resolve particle counting rates as high as 1.5*10/sup 5/ counts/s, and as high as 10/sup 6/ in the pulse height analyzer (PHA) mode. >

Phase locked loop circuit and semiconductor integrated circuit using the phase locked loop circuit

Abstract: A PLL circuit is operatively coupled to a power source and comprises a phase comparator (2, 3) for comparing phases of an input signal and a feedback signal, a memory (7, 8) for storing information related to the input signal, a control voltage output circuit (15) for outputting a control voltage based on the information read out from the memory, and a feedback loop circuit (4, 5, 10) including a voltage controlled oscillator (5) whose oscillation frequency is controlled by the control voltage received from the control voltage output circuit. The feedback loop circuit supplies a signal which is derived from an output signal of the voltage controlled oscillator to the phase comparator as the feedback signal. The use of the memory means (7, 8) allows the PLL circuit to lock to a target frequency within a short time regardless of the time constant of the feedback loop.

ECL to CMOS level conversion circuit

Abstract: A level conversion circuit includes an input buffer receiving an ECL level signal, a current mirror circuit receiving the output of the input buffer and a reference voltage and providing a converted CMOS level output signal, and a reference voltage generating circuit. The reference voltage generating circuit includes either a circuit for simulating at least portions of the input buffer, or it includes a circuit for providing a reference voltage to the current mirror circuit which varies in accordance with the level of the input signal.

Digital-analog converter including a reduced number of resistors arranged in a string

Abstract: A digital-analog converter according to the invention comprises a resistance circuit including a plurality of resistors connected in series, a switching circuit including a plurality of switching element disposed between the resistance circuit and an analog output terminal, a control-signal generating circuit for selectively turning on and off the switching elements, and a change-over circuit for switching the resistance circuit. The resistance circuit includes a first resistor having a resistance value of one half a unit resistance value and unit resistors of a unit resistance value and connected in series, the number of unit resistors provided being expressed by 2 to the (n-1)th power. The change-over circuit functions to connect resistors having a unit resistance value in parallel with selected unit resistors in the resistance circuit by means of changing switches which are selectively turned on and off by the control-signal generating circuit.

Flip-flop circuit for scan cell

Abstract: PURPOSE:To provide the scan cell use flip-flop circuit in which current consumption is reduced by preventing a through-current from flowing to a scan-out circuit and a scan-in circuit of the scan cell use FF circuit connecting to a next stage after a scan-out control signal is cleared CONSTITUTION:The scan cell flip-flop circuit having a master/slave D flip-flop circuit 10, a scan-in circuit 21 connected between a scan-in terminal SI and a data latch circuit at the master side of the D FF circuit 10, and a scan-out circuit 22 connected between a scan-out terminal SO and a data latch circuit at the slave side of the D FF circuit 10 is provided with a clocked inverter circuit 23 controlled by a scan-in control signal as an input stage of the scan-in circuit 21 and a clocked inverter circuit 25 controlled by a scan-out control signal as an output stage of the scan-out circuit 22

Semiconductor integrated circuit having means for suppressing a variation in a threshold level due to temperature variation

Abstract: A semiconductor integrated circuit includes an input circuit having a CMOS inverter and receiving an input signal. The input circuit has a threshold level which determines an output level of the input circuit with respect to the input signal. The integrated circuit includes an internal circuit receiving the input signal via the input circuit, the internal circuit receiving a first power supply voltage. A power source generates a second power supply voltage applied to the input circuit so that the second power supply voltage changes to cancel a change in the threshold level due to a temperature variation.

A parasitics extraction and network reduction algorithm for analog VLSI

Abstract: A transmission line model for the extraction of circuit parasitics in integrated circuits is presented. This model is shown to give a better account of the DC and aC characteristics of interconnects than models incorporating exclusively the R or C components. A network-reduction technique that is used to simplify the extracted RC network at user-specified accuracies to manageable complexities, especially for large VLSI circuits, is also discussed. The model and circuit reduction algorithms are applied to practical sample circuits and results of simulations illustrating the reduction in circuit complexity and the degree of modeling accuracy by these methods are given. >

Integrated circuit device of remote control type for driving a D.C. motor

Abstract: An integrated circuit for driving a d.c. motor for use in a device, such as a toy car. The device include a noise filtering circuit, a pulse expansion circuit, a first oscillator, a second oscillator power voltage reset circuit, a constant voltage supplying circuit, a voltage detector, an inherent code input circuit, a right and left lamp driving circuit, a frequency dividing circuit, an inherent code detecting circuit, a received signal detecting circuit, an error signal detecting circuit, a comparator, a demodulator, a one-shot circuit, a servo-motor driving circuit, a speed variable driving circuit and an additional function driving circuit. Accordingly, a shared frequency can be utilized by a large number of people having an inherent code operably integrated. In addition, the variation of speed and position of the motor can be controlled in multi-steps, and the respective external elements can be minimized in size and erroneous device operation significantly reduced.

Constant current circuit and an oscillating circuit controlled by the same

Abstract: A constant current circuit having an output current I 2 which changes with the change of the power source voltage V cc , and an oscillating circuit whose oscillation frequency is made variable by the change of I 2 in the constant current circuit. The constant current circuit comprises bipolar transistors coupled to form a differential amplifier, wherein one of the transistors is supplied with a reference voltage and another is supplied with a divided voltage of V cc , and a resistor connecting the emitters of the transistors is provided for controlling the slope of the V cc -I 2 characteristic curve of the constant current circuit. The oscillating circuit comprises a capacitor charged with I 2 and a switching circuit for discharging the capacitor when it is closed and a voltage detecting circuit operating to close or open the switching circuit according to the detection of the voltage at an end of the capacitor. Thus, the switching circuit operates on and off to generate pulses with frequency depending on I 2 , hence, depending on V cc . Methods for controlling the frequency range of the oscillating circuit and the rise time to fall time ratio of the pulses by introducing additional constant current supplying sources are also disclosed.