Showing papers on "Sequential logic published in 1990"

Sequential circuit verification using symbolic model checking

Abstract: The temporal logic model algorithm of E.M. Clarke et al. (ACM Trans. Prog. Lang. Syst., vol.8, no.2, p.244-63, 1986) is modified to represent a state graph using binary decision diagrams (BDDs). Because this representation captures some of the regularity in the state space of sequential circuits with data path logic, one is able to verify circuits with an extremely large number of states. This new technique is demonstrated on a synchronous pipelined design with approximately 5*10/sup 20/ states. The logic that is used to specify circuits is a propositional temporal logic of branching time, called CTL or Computation Tree Logic. The model checking algorithm handles full CTL with fairness constraints. Consequently. it is possible to handle a number of important liveness and fairness properties. which would otherwise not be expressible in CTL. The method presented is not necessarily a replacement for brute-force state-enumeration methods but an alternative that may work efficiently when the brute force methods fail. >

A partial scan method for sequential circuits with feedback

Abstract: A method of partial scan design is presented in which the selection of scan flip-flops is aimed at breaking up the cyclic structure of the circuit. Experimental data are given to show that the test generation complexity may grow exponentially with the length of the cycles in the circuit. This complexity grows only linearly with the sequential depth. Graph-theoretic algorithms are presented to select a minimal set of flip-flops for eliminating cycles and reducing the sequential depth. Tests for the resulting circuit are generated by a sequential logic test generator. An independent control of the scan clock allows insertion of scan sequences within the vector sequence produced by the test generator. An independent control of the scan clock allows insertion of scan sequences within the vector sequences produced by the test generator. 98% fault coverage is obtained for a 5000-gate circuit by scanning just 5% of the flip-flops. >

NOVA: state assignment of finite state machines for optimal two-level logic implementation

Abstract: The problem of encoding the states of a synchronous finite state machine (FSM) so that the area of a two-level implementation of the combinational logic is minimized is addressed. As in previous approaches, the problem is reduced to the solution of the combinatorial optimization problems defined by the translation of the cover obtained by a multiple-valued logic minimization or by a symbolic minimization into a compatible Boolean representation. The authors present algorithms for this solution, based on a novel theoretical framework that offers advantages over previous approaches to develop effective heuristics. The algorithms are part of NOVA, a program for optimal encoding of control logic. Final areas averaging 20% less than other state assignment programs and 30% less than the best random solution have been obtained. Literal counts averaging 30% less than the best random solutions have been obtained. >

On determining scan flip-flops in partial-scan designs

Abstract: A report is presented on procedures investigated to determine flip-flops to be scanned in partial-scan designs for sequential circuits. The main idea pursued is to derive a minimal feedback vertex set of the so-called S-graphs. Results of applying optimal and heuristic procedures on a set of benchmark circuits indicate that heuristic methods give fast and near minimal solutions. >

Logic synthesis for programmable gate arrays

Abstract: The problem of combinational logic synthesis is addressed for two interesting and popular classes of programmable gate array architecture: table-lookup and multiplexer-based. The constraints imposed by some of these architectures require new algorithms for minimization of the number of basic blocks of the target architecture, taking into account the wiring resources. The presented algorithms are general and can be used for both of the above-mentioned architectures. >

PROOFS: a fast, memory efficient sequential circuit fault simulator

Abstract: A super-fast fault simulator for synchronous sequential circuits, called PROOFS, is described. PROOFS achieves high performance by combining all the advantages of differential fault simulation, single fault propagation, and parallel fault simulation, while minimizing their individual disadvantages. PROOFS minimizes the memory requirements, reduces the number of events that need to be evaluated, and simplifies the complexity of the software implementation. PROOFS requires an average of one fifth the memory required for concurrent fault simulation and runs 6 to 67 times faster on the ISCAS sequential benchmarks. >

An optimization based approach to the partial scan design problem

Abstract: The problem of selecting flip-flops for inclusion into a partial scan path is formulated as an optimization problem. Scan flip-flops result in layout and delay overheads. Hence, scan flip-flops have to be chosen such that the net cost associated with these overheads is bounded by some user-specified limit. The problem then reduces to choosing a set of flip-flops which gives the best improvement in testability, while keeping the cost bounded. Cost functions are proposed for a standard cell design approach to model the effects of the overheads. Profit functions for three different testability criteria are proposed, and the optimization methodology for each is discussed. The optimization process is modeled on the lines of the 0/1 knapsack problem. Results for some medium-sized sequential circuits which show a very large improvement in fault coverage obtained by optimally selecting a small fraction of the flip-flops in the circuit are presented. >

An analytical approach to the partial scan problem

Abstract: The scan design is the most widely used technique used to ensure the testability of sequential circuits. In this article it is shown that testability is still guaranteed, even if only a small part of the flipflops is integrated into a scan path. An algorithm is presented for selecting a minimal number of flipflops, which must be directly accessible. The direct accessibility ensures that, for each fault, the necessary test sequence is bounded linearly in the circuit size. Since the underlying problem is NP-complete, efficient heuristics are implemented to compute suboptimal solutions. Moreover, a new algorithm is presented to map a sequential circuit into a minimal combinational one, such that test pattern generation for both circuit representations is equivalent and the fast combinational ATPG methods can be applied. For all benchmark circuits investigated, this approach results in a significant reduction of the hardware overhead, and additionally a complete fault coverage is still obtained. Amazingly the overall test application time decreases in comparison with a complete scan path, since the width of the shifted patterns is shorter, and the number of patterns increase only to a small extent.

System for fast selection of non-cacheable address ranges using programmed array logic

Abstract: A fast logic system for decoding addresses for the purpose of designating areas of memory as non-cacheable is disclosed. The logic system is based on a programmable array logic having as inputs selected address lines, certain switch settings, and software-selectable diagnostic settings.

Irredundant sequential machines via optimal logic synthesis

Abstract: It is shown that optimal sequential logic synthesis can produce irredundant, fully testable finite-state machines. Synthesizing a sequential circuit from a state transition graph description involves the steps of state minimization, state assignment, and logic optimization. Previous approaches to producing fully and easily testable sequential circuits have involved the use of extra logic and constraints on state assignments and logic optimization. Here it is shown that 100% testability can be ensured without the addition of extra logic and without constraints on the state assignment and logic optimization. Unlike previous synthesis approaches to ensuring fully testable machines, there is no area/performance penalty associated with this approach. This technique can be used in conjunction with previous approaches to ensure that the synthesized machine is easily testable. Given a state-transition-graph specification, a logic-level automaton that is fully testable for all single stuck-at faults in the combinational logic without access to the memory elements is synthesized. >

Formal Verification of Digital Circuits Using Symbolic Ternary System Models

Abstract: Ternary system modeling involves extending the traditional set of binary values {0, 1} with a third value X indicating an unknown or indeterminate condition. By making this extension, we can model a wider range of circuit phenomena. We can also efficiently verify sequential circuits in which the effect of a given operation depends on only a subset of the total system state.

A logic of concrete time intervals

Abstract: A description is given of: (1) a finite-state model for asynchronous systems in which the time delays between the scheduling and occurrence of the events that cause state changes are constrained to fall between fixed numerical upper and lower time bounds; (2) a branching-time temporal logic suitable for describing the temporal and logical properties of asynchronous systems, for which the structures of (1) are the natural models; and (3) a functional verification system for asynchronous circuits which generates, from a Boolean circuit with general feedback and specified min/max rise and fall times for the gates, a finite-state structure as in (1), and then exhaustively checks a formal specification of that circuit in the language (2) against that finite-state model. >

Functional test generation for finite state machines

Abstract: A functional test generation method for finite-state machines is described. A functional fault model, called the single-transition fault model, on the state transition level is used. In this model, a fault causes a single transition to a wrong destination state. A fault-collapsing technique for this fault model is also described. For each state transition, a small subset of states is selected as the faulty destination states so that the number of modeled faults for test generation is minimized. On the basis of this fault model, the authors developed an automatic test generation algorithm and built a test generation system. The effectiveness of this method is shown by experimental results on a set of benchmark finite-state machines. A 100% stuck-at fault coverage is achieved by the proposed method for several machines, and a very high coverage (>97%) is also obtained for other machines. In comparison with a gate-level test generator STG3, the test generation time is speeded up by a factor of 100. >

Don't care minimization of multi-level sequential logic networks

Abstract: The authors address the problem of computing sequential don't cares that arise in the context of multi-level sequential networks and their use in sequential logic synthesis. The key to their approach is the use of binary decision diagram (BDD)-based implicit state space enumeration techniques and multi-level combinational simplification procedures. Using the algorithms described, exact sequential don't care sets for circuits with over 10/sup 68/ states have been successfully computed. >

A depth-decreasing heuristic for combinational logic; or how to convert a ripple-carry adder into a carry-lookahead adder or anything in-between

Abstract: This paper describes a heuristic for speeding up combinational logic by decreasing the logic depth, at the expense of a minimal increase in circuit size. The heuristic iteratively speeds up sections of the critical path by the use of Shannon factorization on the late input. This procedure is empirically found to be capable of reproducing or even beating several classic global optimizations: a chain of an associative operator is transformed into a tree, a ripple prefix circuit into a parallel prefix circuit, and a ripple-carry adder into a slightly smaller and faster circuit than the carry-lookahead adder.

Self-Timed Control of Concurrent Processes: The Design of Aperiodic Logical Circuits in Computers and Discrete Systems

Abstract: 1 Introduction- 2 Asynchronous processes and their interpretation- 21 Asynchronous processes- 211 Definition- 212 Some subclasses- 213 Reposition- 214 Structured situations- 215 An asynchronous process as a metamodel- 22 Petri nets- 221 Model description- 222 Some classes- 223 Interpretation- 23 Signal graphs- 24 The Muller model- 25 Parallel asynchronous flow charts- 26 Asynchronous state machines- 27 Reference notations- 3 Self-synchronizing codes- 31 Preliminary definitions- 32 Direct-transition codes- 33 Two-phase codes- 34 Double-rail code- 35 Code with identifier- 36 Optimally balanced code- 37 On the code redundancy- 38 Differential encoding- 39 Reference notations- 4 Aperiodic circuits- 41 Two-phase implementation of finite state machine- 411 Matched implementation- 42 Completion indicators and checkers- 43 Synthesis of combinatorial circuits- 431 Indicatability- 432 Standard implementations- 4321 Minimum form implementation- 4322 Orthogonal form implementation- 4323 Hysteresis flip-flop-based implementation- 4324 Implementation based on "collective responsibility"- 44 Aperiodic flip-flops- 441 Further discussion of flip-flop designs- 4411 RS-flip-flops- 4412 D-flip-flops- 4413 T-flip-flops- 45 Canonical aperiodic implementations of finite state machines- 451 Implementation with delay flip-flops- 452 Implementation using flip-flops with separated inputs- 453 Implementation with complementing flip-flops- 46 Implementation with multiple phase signals- 47 Implementation with direct transitions- 48 On the definition of an aperiodic state machine- 49 Reference notations- 5 Circuit modelling of control flow- 51 The modelling of Petri nets- 511 Event-based modelling- 512 Condition-based modelling- 52 The modelling of parallel asynchronous flow charts- 521 Implementation of standard fragments- 522 A multiple use circuit- 523 A loop control circuit- 524 Using an arbiter- 525 Guard-based implementation- 53 Functional completeness and synthesis of semi-modular circuits- 531 Formulation of the problem- 532 Some properties of semi-modular circuits- 533 Perfect implementation- 534 Simple circuits- 535 The implementation of distributive and totally sequential circuits- 54 Synthesis of semi-modular circuits in limited bases- 55 Modelling pipeline processes- 551 Properties of modelling pipeline circuits- 5511 Pipelinization of parallel fragments- 5512 Pipelinization of a conditional branch- 5513 Transformation of a loop- 5514 Pipelinization for multiply-used sections- 56 Reference notations- 6 Composition of asynchronous processes and circuits- 61 Composition of asynchronous processes- 611 Reinstated process- 612 Process reduction- 613 Process composition- 62 Composition of aperiodic circuits- 621 The Muller theorem- 622 The generalization of the Muller theorem- 63 Algebra of asynchronous circuits- 631 Operations on circuits- 632 Laws and properties- 633 Circuit transformations- 634 Homological algebras of circuits- 64 Reference notations- 7 The matching of asynchronous processes and interface organization- 71 Matched asynchronous processes- 72 Protocol- 73 The matching asynchronous process- 74 The T2 interface- 741 General notations- 742 Communication protocol- 743 Implementation- 75 Asynchronous interface organization- 751 Using the code with identifier- 752 Using the optimally-balanced code- 7521 Half-byte data transfer- 7522 Byte data transfer- 7523 Using non-balanced representation- 76 Reference notations- 8 Analysis of asynchronous circuits and processes- 81 The reachability analysis- 82 The classification analysis- 83 The set of operational states- 84 The effect of non-zero wire delays- 85 Circuit Petri nets- 86 On the complexity of analysis algorithms- 87 Reference notations- 9 Anomalous behaviour of logical circuits and the arbitration problem- 91 Arbiters- 92 Oscillatory anomaly- 93 Meta-stability anomaly- 94 Designing correctly-operating arbiters- 95 "Bounded" arbiters and safe inertial delays- 96 Reference notations- 10 Fault diagnosis and self-repair in aperiodic circuits- 101 Totally self-checking combinational circuits- 102 Totally self-checking sequential machines- 103 Fault detection in autonomous circuits- 104 Self-repair organization for aperiodic circuits- 105 Reference notations- 11 Typical examples of aperiodic design modules- 111 The JK-flip-flop- 112 Registers- 113 Pipeline registers- 1131 Non-dense registers- 1132 Semi-dense pipeline register- 1133 Dense pipeline registers- 1134 One-byte dense pipeline register- 1135 Pipeline register with parallel read-write and the stack- 1136 Reversive pipeline registers- 114 Converting single-rail signals into double-rail ones- 1141 Parallel register with single-rail inputs- 1142 Input and output heads of pipeline registers- 115 Counters- 116 Reference notations- Editor's Epilogue- References

Programmable gate array with logic cells having configurable output enable

Abstract: A configurable logic array, includes a plurality of configurable logic cells which include a tristate output buffer, having an input receiving a logic signal from within the configurable logic cell, an output connected to the configurable interconnect structure and an output enable input. A plurality of selectors, controlled by the configuration memory, supply output enable signals for controlling corresponding tristate output buffers. The inputs to the plurality of selectors include a "common output enable signal," and at least a second logic signal, such as a constant high or constant low logic level. A circuit responsive to program data in the configuration memory and input signals from the interconnect structure generates the common output enable signal. One input of the selector is provided by an invertor connected from the input of the tristate output buffer to the selector for connecting an output signal to a long line in a wired-AND configuration.

Comparison and verification system for logic circuits and method thereof

Abstract: When a hierarchy design is attempted in a logic design of a logic circuit, a system for verifying an equivalence between an upper level logic and a lower level logic is required. When the two different level logics are compared, the logics are once converted to Boolean expressions regardless of logic expressions of the logics, involving a logic circuit diagram and a truth table, and Shannon's formula is applied to the two Boolean expressions under a same order of variables to be extracted, to thereby produce binary decision diagrams (BDDs). When the equivalence between the produced BDDs is determined, the BDDs are simplified, respectively, and the simplified BDDs are integrated from the branches, and a determination can be carried out one time, i.e, without a repeat process.

An algorithm for locating logic design errors

Abstract: Discusses the problem of locating logic design errors, and proposes an algorithm to solve it. Based on the results of logic verification, the authors introduce an input pattern for locating design errors. The pattern contains only one Boolean variable X/X and is used to sensitize the design errors. An algorithm for locating single design errors with the input patterns has been developed. Experimental results have shown the effectiveness of the input patterns and the algorithm for locating single design errors. >

High speed logic simulation system with stimulus engine using independent event channels selectively driven by independent stimulus programs

Abstract: A stimulus engine for a logic simulation system is used to interpret a stimulus language and generate test patterns as input to a logic simulator. The stimulus language allows a large test pattern set to be represented as a program. Special purpose hardware interprets this program and generates a sequence of input/output events to the logic simulator. The program interpretation is performed while the logic simulation is executing. Special purpose hardware is used to insure that the stimulus engine is able to generate the input/output events at a rate which does not slow down the logic simulator.

Differential fault simulation for sequential circuits

Abstract: A new fast fault simulation algorithm called differential fault simulation, DSIM, for synchronous sequential circuits is described. Unlike concurrent fault simulation, for every test vector, DSIM simulates the good machine and each faulty machine separately, one after another, rather than simultaneously simulating all machines. Therefore, DSIM dramatically reduces the memory requirement and the overhead in the memory management in concurrent fault simulation. Also, unlike serial fault simulation, DSIM simulates each machine by reprocessing its differences from the previously simulated machine. In this manner, DSIM is more efficient than serial fault simulation. Experiments have shown that DSIM runs 3 to 12 times faster than an existing concurrent fault simulator. In addition, owing to the simplicity of this algorithm, DSIM is very easy to implement and maintain. An implementation consists of only about 300 lines of “C” language statements added to the event-driven true-value simulator in an existing sequential circuit test generator program, STG3. Currently DSIM uses the zero-delay timing model. The addition of alternative delay models is under development.

Retiming and resynthesis: optimizing sequential networks with combinational techniques

Abstract: A technique is proposed for optimizing a sequential network by moving the registers to the boundary of the network using an extension of retiming, resynthesizing the combinational logic between the registers using existing logic minimization techniques, and replacing the registers throughout the network using retiming algorithms. A sliding-window optimization technique that considers a large number of different combinational blocks is proposed and demonstrated. The theoretical formulation and results on which the approach is based are given. >

Tautology checking using cross-controllability and cross-observability relations

Abstract: A novel method is described for verifying the equivalence between a combinational circuit and its specification, when both are given in a modular (e.g., factored) form. It is based on the notion of cross-controllability and cross-observability relations that exist between the internal logic values across a cut of the joint composition of the circuit and the specification. It is proven that even after abstracting input and other internal variables the relations are sufficient to verify the equivalence. The abstraction allows reduction of the size of the relation, thus permitting the verification of much larger circuits. A report is presented on the verification of an 8*8 parallel multiplier using at most 527 BDD (binary decision diagram) cells of 21 variables. Extensions to sequential circuits are also discussed. >

Modular, electronic safe-arm device

Abstract: A modular electronic safe arm device (MESAD) (10) for arming and igniting an explosive is universal in application and employs a standard circuit architecture which uses application specific logic modules (12) and (14), a standard voltage control module (16), and standard high energy firing modules (18) and (20). In the preferred embodiment, the logic modules (12) and (14) are state machines using clocked sequential logic and having read-only-memories. The logic modules (12) and (14) generate dynamic arming signals at outputs (54) and (76) which cause the voltage control module (16) in conjunction with transformer (102), to convert a low voltage input (98) to a high voltage output (100). The high voltage output (100) is used to charge firing capacitors (112) and (138) in standard high energy firing modules (18) and (20). Logic module (14) generates two trigger signals at outputs (76) and (78) for activating the trigger modules (126) and (148). Charging and triggering of the high energy firing modules (18) and (20) causes explosive foil initiators (108) and (134) to ignite the explosive. Application specific interface units (40) and (86) allow the MESAD (10) to be used in many different applications.

Noise reducing output buffer circuit for an integrated circuit

Abstract: An output buffer circuit for an integrated circuit for outputting an amplified signal from a sense amplifier which senses information stored in a memory cell of random access memory for improving operation of the integrated circuit is disclosed The output buffer circuit comprises NAND gates ND1, ND2 operatively connected to the output of the sense amplifier to receive first and second output signals S1, S2, and operatively connected to receive a control signal φ1 from the integrated circuit which operates the memory cell to read A MOSFET Q1 and a MOSFET Q2 are utilized with both MOSFETs turning on or off depending upon the signals applied to their gates An output loading capacitor CL is operatively connected to the junction P4 and to the ground A logic combination means 10 connected to junctions P1, P2 performs a logical combination of the signal applied through the junction P4 and the control signal φ1 applied to the input points of the logic combination means An output means 20 is connected between the logic combination means 10 and the junction P4, thereby controlling the output level of the output buffer circuit to a middle level depending upon the signal from the logic combination means

Synthesis of combinational logic circuits for path delay fault testability

Abstract: An approach to the design of multilevel, multi-output combinational logic circuits in which all path delay faults are detectable by robust tests is proposed. Inadequacies of previous approaches for synthesis for testability of path delay faults are discussed. A necessary and sufficient condition for the existence of a hazard-free robust test for a path is stated. Violation of this condition is adopted as the criterion for identifying the paths, in a given circuit, which are not testable by hazard-free robust tests. Transformation methods to render these paths testable are proposed. >

High level test generation using data flow descriptions

Abstract: To significantly expedite the test generation process for sequential VLSI circuits, the hierarchy in the circuit descriptions should be exploited. Conventional test generators can provide tests for relatively small modules, which are typically embedded in large circuits. This paper considers test generation for complex VLSI circuits composed of many interconnected modules. In contrast to the previous approaches, the authors use high-level primitives and data flow descriptions to perform hierarchical test generation. Data flow descriptions provide the set of valid control signals to be activated for a particular data path to be active. Sequential propagation and justification of signals is carried out recursively. Results are presented based on an implementation of the algorithm in LISP on a Texas Instruments Explorer. >

Process monitor circuit

Abstract: In accordance with the present invention, a process monitor circuit and a method for monitoring a process are provided. The process monitor circuit provides first and second logic paths, the first logic path having a delay sensitive to whether the input logic transition is from logic high to logic low, or from logic low to logic high. The second logic path has substantially equal delays for either logic state transition. The two differences in delay between the first and second logic paths under the two logic state transitions are used to monitor the process steps for manufacturing the P and N transistors.

A unified approach to the decomposition and re-decomposition of sequential machines

Abstract: We present a unified framework and associated algorithms for the optimal decomposition and re-decomposition of sequential machines. This framework allows for a uniform treatment of arbitrary decomposition topologies operating at the State Transition Graph (STG) level, while targeting a cost function that is close to the eventual logic implementation. Previous work has targeted specific decomposition topologies via the formulation of decomposition as implicant covering with associated constraints. It is shown that this formulation can be used to target arbitrary desired topologies merely by customizing the constraints during implicant covering. It is shown how this work relates to preserved partitions and covers traditionally used in parallel and cascade decomposition, and how this formulation establishes the relationship between state assignment and FSM decomposition.In many cases, an initial decomposition is specified as a starting point. Attempting to flatten a set of interacting circuits into a single lumped STG in order to modify the decomposition structure could require astronomical amounts of CPU time and memory. Memory and CPU time efficient re-decomposition algorithms that operate on distributed-style specifications and which are more global than those presented in the past have been developed. These algorithms have been implemented in the sequential logic synthesis system, FLAMES, that is being developed at UCB/MIT.

PROOFS: a super fast fault simulator for sequential circuits

Abstract: This paper describes PROOFS, a super fast fault simulator for synchronous sequential logic circuits. PROOFS achieves high performance by combining all the advantages in differential fault simulation, single fault propagation, and parallel fault simulation to minimize the memory requirements, to reduce events that need to be simulated, and to simplify the complexity of the software implementation. The experimental results of PROOFS and other available fault simulators on 20 benchmark circuits showed that PROOFS is the best. >