Showing papers on "Snapback published in 1995"

Capacitor couple electrostatic discharge protection circuit

Abstract: The present invention is related to a capacitor-couple electrostatic discharge (ESD) protection circuit for protecting an internal circuit and/or an output buffer of an IC from being damaged by an ESD current. The capacitor-couple ESD protection circuit according to the present invention includes an ESD bypass device for bypassing the ESD current, a capacitor-couple circuit for coupling a portion of voltage to the ESD bypass device, and a potential leveling device for keeping an ESD voltage transmitted for the internal circuit at a low potential level. By using the present ESD protection circuit, the snapback breakdown voltage can be lowered to protect the very thin gate oxide of the internal circuit especially in the submicron CMOS technologies.

ESD protection for deep submicron CMOS devices with minimum tradeoff for latchup behavior

Abstract: Apparatus and process for making the apparatus for electrostatic discharge (ESD) protection of an electronic device, using a silicon controlled rectifier (SCR) configuration. A spaced apart p-well and n-well are formed in a substrate, and spaced apart p+ and n+ contact regions are formed in each well, with an additional n+ or p+ drain tap contiguous to and lying between the two wells. The wells may be formed by a retrograde process or by a conventional process, with or without an epitaxial layer. A first electrode (ground) is connected to the p+ and n+ contact regions and through a polysilicon region to a gate oxide region in the first well. The polysilicon region has a small, controlled poly length. A second electrode is connected to the p+ and n+ contact regions in the second well and to an electrical circuit to be protected against ESD. The second well may be replaced by a portion of the substrate, of opposite electrical polarity to the first well. The triggering voltage for snapback of the SCR device is tunable over a voltage range as low as 5-11 Volts, and the device dynamical resistance in the on-state is about 8-9 Ohms. The SCR device has reduced tradeoff with latchup behavior of the electronic device to be protected.

CMOS output buffer with enhanced high ESD protection capability

Abstract: An ESD protection circuit for use in a CMOS output buffer circuit has been disclosed. The ESD protection circuit provides a high ESD failure threshold in a small layout area to protect the output buffer against ESD failure. The output buffer includes a pull-up PMOS device and pull-down NMOS device whose common drain is connected to an output pad. The source of the PMOS device is connected to VDD and the source of NMOS device is connected to VSS. The ESD protection circuit is formed by a PTLSCR device and an NTLSCR device. The PTLSCR (NTLSCR) is formed by inserting a short-channel thin-oxide PMOS (NMOS) device into a lateral SCR structure. These MOS devices reduce the turn-on voltage of the lateral SCR to the snapback breakdown voltage of the MOS rather than the original switching voltage of the SCR. The ESD protection circuit also includes two parasitic diodes D p between output pad and VDD and D n between output pad and VSS. The four modes of ESD, PS, NS, PD and ND, are one-by-one protected by NTLSCR, Dn, Dp and PTLSCR, respectively.

High resolution active matrix lcd cell design

Abstract: A transistor panel used for active matrix display devices includes islands of single crystal silicon formed on a transparent quartz substrate and arranged in rows and columns, with an NMOS transistor formed in each island. Each transistor includes source, drain and channel regions and an isolated pixel reference voltage region. A silicon body tie connects the channel region to the pixel reference voltage region and acts as a current sink for unwanted carriers thereby greatly increasing the snapback voltage. A metallization extends to each transistor and is in contact with each reference voltage region to form a body tie bus. The portion of the body tie that overlaps the pixel electrode may be sized to provide a storage capacitor for improved display performance. The unique body tie design obviates the need for a separate light shield layer, provides a dramatically increased aperture ratio and is compatible with normal high temperature silicon processes.

Electrostatic discharge (ESD) protection structure for high voltage pins

Abstract: An improved input ESD protection structure is disclosed that is suitable for use on high-voltage input pins, such as programming pins, of programmable integrated circuits such as programmable logic devices (PODs) programmable read-only memories (PROMs), or field programmable gate arrays (FPGAs). The input ESD protection structure includes a primary ESD protection FET for shunting ESD current from the input pad, and a secondary ESD protection FET, in combination with a series resistor, to limit the voltage appearing across the gate oxides of the input buffer. The primary protection FET is laid out in a multi-finger architecture wherein the drain n + -type conductivity regions are overlapped with a depletion implant. The depletion implant extends from these drain regions, respectively, through channel regions toward the source regions. Further, the ESD protection structure is subject to a p-well mask, which blocks the formation of a p-well to thereby reduce background p-type doping to p-substrate doping levels. The depletion implant and p-well protect mask increase the breakdown, and snapback voltages of the primary and secondary FETs to improve ESD immunity. An n-well is disposed underneath the drain region, particularly under the drain contacts, to increase the junction depth in the drain region to thereby minimize contact spiking during an ESD event. The secondary protection FET is integrated with the primary protection FET by using the same n + diffusions as used by the primary ESD protection FET.

Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's

Abstract: There is one LVTSCR (Low Voltage Trigger SCR) device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in a complementary style to offer effective and direct ESD discharging paths from the input or output pads to V/sub SS/ and V/sub DD/ powerlines. The DC switching voltage of LVTSCR devices is lowered to the snapback voltage of short-channel NMOS and PMOS devices. Experimental results show that it has an excellent ESD protection capability in a smaller layout area.

ESD protection elements during HBM stress tests: further numerical and experimental results

Abstract: Correlation problems for HBM-ESD testing result from the complex interaction between device and tester. The HBM stresses of different well-characterized testers 1,2 are applied to protection elements. By means of circuit simulations and in situ measurements, snapback and second breakdown during HBM are investigated. For fast transient events, a new transmission line approach of the tester improves the correlation between experiment and simulation.

On-chip ESD protection using capacitor-couple technique in 0.5-/spl mu/m 3-V CMOS technology

Abstract: Capacitance-coupling effect used to lower snapback voltage and to ensure uniform ESD current distribution in the NMOS/PMOS devices of submicron CMOS on-chip ESD protection circuits is proposed. The couple capacitor is made by a poly layer right under the wire-bonding metal pad without increasing extra layout area to the pad. By using this technique, ESD robustness of submicron CMOS IC's can be significantly improved.

ESD protection elements during HBM stress tests: further numerical and experimental results

Abstract: Correlation problems for HBM-ESD testing result from the complex interaction between device and tester. The HBM stresses of different well-characterized testers 1,2 are applied to protection elements. By means of circuit simulations and in situ measurements, snapback and second breakdown during HBM are investigated. For fast transient events, a new transmission line approach of the tester improves the correlation between experiment and simulation.

Protection circuit against electrostatic discharge with two capacitors

Abstract: The ESD protection circuit includes an ESD bypass device (223) incorporating an NMOS and PMOS transistor for bypassing the ESD current. A capacitor-couple circuit (222) couples a portion of voltage to the ESD bypass device, and a potential levelling device (224) incorporates two diodes for keeping an ESD voltage transmitted for the internal circuit at a low potential level. By using the present ESD protection circuit, the snapback breakdown voltage can be lowered to protect the thinner gate oxide of the internal circuit (23) of the IC.

Melt filaments in n + pn + lateral bipolar ESD protection devices

Abstract: Lateral bipolar n/sup +/pn/sup +/ devices, with thick field oxide (TFO) separating the collector and emitter, are often used in snapback mode as protection devices for MOS ESD circuit protection. ESD testing for Human Body Model (HBM), Machine Model (MM) and Charged Device Model (CDM) waveforms was performed on a family of TFO cells which varied the gate length (bipolar base width) as the experimental parameter. For MM and CDM, the data showed a dependence of withstand voltage on the gate length, indicating that longer gate lengths improve performance; while for HBM, withstand voltage was independent of the gate length. The devices exhibited failure modes that manifested as low level current leakage. Failure analysis identified the current leakage sites as melt filaments primarily localized at the TFO ends. Filament distribution was seen to be a function of gate length for MM. Two possible mechanisms are presented to account for the observed filament distribution and follow up experiments are suggested to test the validity of each.

ESD induced damage and hot-carrier reliability of NMOS and PMOS transistors

Abstract: The Hot-Carrier Induced (HCI) degradation and the Electro-Static Discharge (ESD) induced damage are characterized for evaluating the reliability of both submicron LDD NMOS and PMOS transistors. These two types of transistors show different reliability behaviors in terms of the maximum HCI degradation conditions, the DC lifetimes, the snapback voltage characteristics, and ESD failure threshold voltages. Some observations are also described as unique features in the geometric effects both for HCI degradations in short channel/narrow width regimes and for ESD failure thresholds in the Machine Model (MM) ESD device characterization.