Showing papers on "State (computer science) published in 2007"

A marriage of rely/guarantee and separation logic

Abstract: In the quest for tractable methods for reasoning about concurrent algorithms both rely/guarantee logic and separation logic have made great advances. They both seek to tame, or control, the complexity of concurrent interactions, but neither is the ultimate approach. Relyguarantee copes naturally with interference, but its specifications are complex because they describe the entire state. Conversely separation logic has difficulty dealing with interference, but its specifications are simpler because they describe only the relevant state that the program accesses. We propose a combined system which marries the two approaches. We can describe interference naturally (using a relation as in rely/guarantee), and where there is no interference, we can reason locally (as in separation logic). We demonstrate the advantages of the combined approach by verifying a lock-coupling list algorithm, which actually disposes/frees removed nodes.

Binary Arithmetic

Abstract: Digital technology works so well because at the heart of digital representation, there are only a few basic components. Nowadays, these basic components usually are binary digits, bits for short, called binary because they are designed to stand for only two different values, conveniently called zero and one. A stored or transmitted bit's state can deteriorate quite badly before a processing device will be mistaken in deciding which of the two possible values is the original.

System and method for preventing network misuse

Abstract: A system and method for preventing misuse conditions on a data network are described. Embodiments of the system and method evaluate potential network misuse signatures by analyzing variables such as the state of the network and/or target, the context in which the potential misuse signatures are detected, the response/reaction of the target and/or the fingerprint of the target. These and other variables may be factored in to the misuse determination, either alone, or in combination.

Building automation system controller

Abstract: A building control system is provided that receives information from devices of different subsystems. A trigger causes a zone controller to store the information in a database. The stored data is used to generate customized reports based on sequences or sets of related events. The information from multiple subsystems is consolidated, analyzed, and patterns of behavior are determined. The trigger also causes execution of control actions throughout the building spanning the multiple subsystems, devices, and areas based on the information. An access control subsystem and a non-access control subsystem of the building control system are linked using a common network such that a change in the state of an access control device can affect the state of a non-access control device and a change in the state of a non-access control device can affect the state of an access control device.

Specification and verification challenges for sequential object-oriented programs

Abstract: The state of knowledge in how to specify sequential programs in object-oriented languages such as Java and C# and the state of the art in automated verification tools for such programs have made measurable progress in the last several years. This paper describes several remaining challenges and approaches to their solution.

Storage Architecture for Virtual Machines

Abstract: Some embodiments of the present invention include a method comprising: accessing units of network storage that encode state data of respective virtual machines, wherein the state data for respective ones of the virtual machines are stored in distinct ones of the network storage units such that the state data for more than one virtual machine are not commingled in any one of the network storage units.

A note on brain actuated spelling with the Berlin brain-computer interface

Abstract: Brain-Computer Interfaces (BCIs) are systems capable of decoding neural activity in real time, thereby allowing a computer application to be directly controlled by the brain. Since the characteristics of such direct brain-to-computer interaction are limited in several aspects, one major challenge in BCI research is intelligent front-end design. Here we present the mental text entry application 'Hex-o-Spell' which incorporates principles of Human-Computer Interaction research into BCI feedback design. The system utilises the high visual display bandwidth to help compensate for the extremely limited control bandwidth which operates with only two mental states, where the timing of the state changes encodes most of the information. The display is visually appealing, and control is robust. The effectiveness and robustness of the interface was demonstrated at the CeBIT 2006 (world's largest IT fair) where two subjects operated the mental text entry system at a speed of up to 7.6 char/min.

Display device with capture capabilities

Abstract: An image capture and display device is described The device includes a liquid crystal display panel, which can switch between two states, a display state and the capture state Wherein at least a portion of the display and a switchable diffuser become transparent in the capture state One or more image capture devices are located behind the display Holes or windows are provided in the backlight for the image capture devices to capture images of the scene in front of the device when in the capture state

Implementation of Virtual Machine Operations Using Storage System Functionality

Abstract: One embodiment of the present invention includes a method comprising: (a) representing at least state data of a virtual machine in a unit of network storage of a network storage system; and (b) employing data manipulation functionality of the network storage system to implement a virtual machine operation that manipulates at least the state data of the virtual machine.

Current compliant sensing architecture for multilevel phase change memory

Abstract: A memory device and a method of reading the same includes a phase change element having a data state associated therewith that features maintaining the consistency of the data state of the phase change element in the presence of a read current. The memory circuit includes a sense amplifier that defines a sensing node. Circuitry selectively places the bit line in data communication with the sensing node, defining a selected bit line. A current source produces a read current, and a switch selectively applies the read current to the sensing node. Logic is in electrical communication with the sensing node to control the total energy to which the phase change material is subjected in the presence of the read current so that the data state remains consistent.

Masking and Dual-Rail Logic Don't Add Up

Abstract: Masked logic styles use a random mask bit to de-correlate the power consumption of the circuit from the state of the algorithm. The effect of the random mask bit is that the circuit switches between two complementary states with a different power profile. Earlier work has shown that the mask-bit value can be estimated from the power consumption profile, and that masked logic remains susceptible to classic power attacks after only a simple filtering operation. In this contribution we will show that this conclusion also holds for masked pre-charged logic styles and for all practical implementations of masked dual-rail logic styles. Up to now, it was believed that masking and dual-rail can be combined to provide a routing-insensitive logic style. We will show that this assumption is not correct. We demonstrate that the routing imbalances can be used to detect the value of the mask bit. Simulations as well as analysis of design data from an AES chip support this conclusion.

Method and apparatus to convert a logical unit from a first encryption state to a second encryption state using a journal in a continuous data protection environment

Abstract: In one aspect, a method to convert a logical unit from a first encryption state to a second encryption state includes receiving a request to convert a logical unit from a first encryption state to a second encryption state, partitioning the logical unit into areas comprising a converted area, an unconverted area and a transition area, writing unconverted data in the transition area to a journal, converting the unconverted data from the first encryption state to the second encryption state and writing the converted data to the logical unit.

Model Checking Markov Chains with Actions and State Labels

Abstract: In the past, logics of several kinds have been proposed for reasoning about discrete-time or continuous-time Markov chains. Most of these logics rely on either state labels (atomic propositions) or on transition labels (actions). However, in several applications it is useful to reason about both state properties and action sequences. For this purpose, we introduce the logic as CSL which provides a powerful means to characterize execution paths of Markov chains with actions and state labels. asCSL can be regarded as an extension of the purely state-based logic CSL (continuous stochastic logic). In asCSL, path properties are characterized by regular expressions over actions and state formulas. Thus, the truth value of path formulas depends not only on the available actions in a given time interval, but also on the validity of certain state formulas in intermediate states. We compare the expressive power of CSL and asCSL and show that even the state-based fragment of asCSL is strictly more expressive than CSL if time intervals starting at zero are employed. Using an automaton-based technique, an asCSL formula and a Markov chain with actions and state labels are combined into a product Markov chain. For time intervals starting at zero, we establish a reduction of the model checking problem for asCSL to CSL model checking on this product Markov chain. The usefulness of our approach is illustrated with an elaborate model of a scalable cellular communication system, for which several properties are formalized by means of asCSL formulas and checked using the new procedure

A TMR Scheme for SEU Mitigation in Scan Flip-Flops

Abstract: Radiation from outer space comprising of charged particles can affect transistors in integrated circuits resulting in a change in the state of transistors. This creates a temporary transient effect that corrupts logic within a circuit, and hence it is called a single event upset (SEU). The SEU if captured may lead to soft error. With the progress of microelectronic technology, the shrinkage of transistor sizes is enabling the integration of more transistors in a circuit, making them more vulnerable to soft errors. Any future attempt toward scaling will have to address the problems of circuit reliability which is affected by the increasing number of failures arising from soft errors. In this paper the authors present a novel register design which can detect and correct soft errors. The authors add a redundant latch to the existing structure of a flip-flop and functional data is simultaneously registered at multiple latches. The content of these multiple latches are fed to a majority voter, and if the content of any of these latches is corrupted by a soft error, it is filtered out through the majority voting circuit. This design provides tolerance over the entire vulnerability region of a flip-flop unlike other published solutions. This design can be operated as a simple scan flip-flop or scan hold flip-flop and thus is useful for system testability purposes. The detection and correction operation takes place concurrently, with 23% degradation in system performance

Implicitly parallel programming models for thousand-core microprocessors

Abstract: This paper argues for an implicitly parallel programming model for many-core microprocessors, and provides initial technical approaches towards this goal. In an implicitly parallel programming model, programmers maximize algorithm- level parallelism, express their parallel algorithms by asserting high-level properties on top of a traditional sequential programming language, and rely on parallelizing compilers and hardware support to perform parallel execution under the hood. In such a model, compilers and related tools require much more advanced program analysis capabilities and programmer assertions than what are currently available so that a comprehensive understanding of the input program's concurrency can be derived. Such an understanding is then used to drive automatic or interactive parallel code generation tools for a diverse set of parallel hardware organizations. The chip-level architecture and hardware should maintain parallel execution state in such a way that a strictly sequential execution state can always be derived for the purpose of verifying and debugging the program. We argue that implicitly parallel programming models are critical for addressing the software development crises and software scalability challenges for many-core microprocessors.

Method and apparatus for run-time in-memory patching of code from a service processor

Abstract: Methods and apparatuses enable in-memory patching of a program loaded in volatile memory. A service processor identifies a program to be patched and an associated patch for the program. The patch is loaded into memory, including applying relocation fix-ups to the patch. The service processor directs the program to the patch in place of the segment of the program to be patched. The program implements the patch while maintaining program state, and without suspending execution of the program.

$Z$ -Source Current-Type Inverters: Digital Modulation and Logic Implementation

Abstract: Traditionally, current source (CS) inverters have been adopted for use in medium and high power industry applications. These inverters, however, support only current-buck dc-ac power conversion and need a relatively complex modulator, as compared to conventional voltage source (VS) inverters. To address these limitations, this paper presents an integration of the buck-boost Z-source power conversion concept to the CS inverter topology to develop single- and three-phase Z-source CS inverters. For their efficient control, the paper starts by evaluating different carrier-based reference formulations to identify different inverter state placement possibilities. The paper then proceeds to design appropriate "reference-to-switch" assignments or logic equations for mapping out the correct CS gating signals, allowing a simple carrier-based modulator to control a Z-source CS inverter with complications such as commutation difficulties and "many-to-many" state assignments readily resolved. The developed system can be implemented using a digital signal processor with an embedded VS pulse-width modulator and an external programmable logic device, hence offering a competitive solution for medium power single and three-phase buck-boost power conversion. Theory, simulation, and experimental results are presented in the paper

Securing Virtual Machine Data

Abstract: One embodiment of the present invention is a method including: (a) representing virtual primary disk data and state data of a virtual machine in a unit of storage; (b) exposing the virtual primary disk data of the virtual machine to a guest of the virtual machine to allow the guest to access the virtual primary disk data; and (c) preventing the guest from accessing the state data for the virtual machine.

Coarse/fine program verification in non-volatile memory using different reference levels for improved sensing

Abstract: Coarse/fine programming of non-volatile memory is provided in which memory cells are programmed at a first rate of programming prior to reaching a coarse verify level for their intended state and a second rate of programming after reaching the coarse verify level but before reaching the final verify level for their intended state. Large sub-threshold swing factors associated with smaller memory cells can affect the accuracy of sense operations, particularly when sensing at a fine verify level after sensing at a coarse verify level without pre-charging the bit line between the different sensings. Different reference potentials are utilized when sensing at a coarse verify level and a final verify level. The different between the reference potentials can compensate for any discharge of the bit line during the coarse level sensing.

Pavement Resurfacing Planning for Highway Networks: Parametric Policy Iteration Approach

Abstract: This paper presents a modeling framework for planning pavement resurfacing activities on highway networks in the case of continuous pavement state, discrete time, and infinite horizon. Optimal resurfacing policies that minimize discounted life-cycle costs are obtained by solving a multidimensional dynamic program, where travelers’ route choices and the agency’s resource allocation decisions are considered simultaneously. To reduce computational difficulty, policy iteration is used together with a parametric function approximation technique. Numerical examples show that the proposed approach solves the planning problem efficiently. The effect of various factors (travelers’ route choice, agency budget, etc.) on the optimal policies is also analyzed.

Method and apparatus for improving responsiveness of a power management system in a computing device

Abstract: A computer system has multiple performance states. The computer system periodically determines utilization information for the computer system and adjusts the performance state according to the utilization information. If a performance increase is required, the computer system always goes to the maximum performance state. If a performance decrease is required, the computer system steps the performance state down to a next lower performance state.

Abstracting Symbolic Execution with String Analysis

Abstract: Forward symbolic execution is a technique for program analysis that explores the execution paths of a program by maintaining a symbolic representation of the program state. Traditionally, applications of this technique have focused on symbolically representing only primitive data types, while more recent extensions have expanded to reference types. We demonstrate the ability to symbolically execute a commonly used library class, specifically a string, at an abstract level. By abstracting away the implementation details of strings using finite-state automata, symbolic execution can scale to more complex programs. This technique can be applied to programs which generate complicated strings, such as SQL database queries.

Automatic State-Based Test Generation Using Genetic Algorithms

Abstract: Although a lot of research has been done in the field of state-based testing, the automatic generation of test cases from a functional specification in the form of a state machine is not straightforward. This paper investigates the use of genetic algorithms in test data generation for the chosen paths in the state machine, so that the input parameters provided to the methods trigger the specified transitions.

Image capture and display control apparatus, image capture and display control method, and image capture and display system

Abstract: The invention provides an image capture and display control apparatus that includes an imaging control unit that operates an image capturing unit at a first time interval so as to obtain a captured image with the image capturing unit and a display control unit that displays the captured image on a display unit, which operates at a second time interval. The apparatus changes at least one of an image capture start timing of the image capturing unit and a processing time from the start of image capturing by the image capturing unit until entering a standby state in which the captured image can be displayed by the display unit, so as to shorten a display delay time, which is caused by the second time interval, from the start of operation by the image capturing unit until display of the image data by the display unit.

Method and system for simulating state retention of an rtl design

Abstract: Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description and the power information specifications, associating the one or more power domains and the power information specifications in the RTL design environment, where the one or more power domains are controlled by a set of power control signals through a power manager logic, and simulating state retention behavior in response to variations in power applied to the power domain.

Additional pins on a USB connector

Abstract: An electronic device includes a receptacle for communicating information via a first communication circuit and a second communication circuit different from the first communication circuit, the receptacle including a plurality of electrically conductive contacts having a predefined arrangement. The electronic device further includes a detection circuit and a configuration circuit. The detection circuit is operatively coupled to at least one of the plurality of contacts, and the detection circuit is operative to detect an electrical state of the at least one contact. The configuration circuit is operatively coupled to a first group of contacts of the plurality of contacts, and the configuration circuit is operative to communicatively couple the first group of contacts to the first communication circuit or the second communication circuit based on the detected state of the at least one contact.

A Game Theoretical Approach for Modelling Merging and Yielding Behavior at Freeway On-Ramp Sections

Abstract: Traffic conflicts between merging and through vehicles are typical phenomena near freeway on-ramp sections, yet fewer microscopic models describing the interaction of these vehicles in the merging process have been proposed. In this paper, vehicle interactions during the merging process are modeled under an enhanced game-theoretic framework. Freeway on-coming through vehicle and on-ramp merging vehicle are considered as competing players that seek to maximize respective rewards during the merging process. As the freeway vehicle aims to maintain their initial car-following state and minimize speed variations, the on-ramp merging vehicle strives to join mainline traffic in the minimal time possible subject to safety constraints. Considering non-cooperative nature of the game, drivers at the merging section would eventually adopt strategies that from Nash equilibrium. To assess the model parameters, the paper proposes a bi-level estimation methodology with the upper level as a least square problem and the lower level a linear complementarity problem searching for the equilibria. Applicability of the proposed model is examined and validated using trajectory data collected from the field. Testing results indicate that this framework can effectively capture vehicle interactions at freeway merging sections while achieving a relatively high accuracy of predicting vehicles’ actions.

Scripted interactive screen media

Abstract: Input from a text editor containing lines of text of a script is received, commands to control objects in a simulation are identified in the lines of text in the editor, a state of the simulation is updated in accordance with the input and the commands, and the simulation is displayed in a graphical display. A computer program enables a user to walk around in a simulation, with the events in the simulation determined by pre-written scripts.

Shared state manager and system and method for collaboration

Abstract: A shared state manager (SSM) for collaboration includes an updating module for updating a shared state of data based on a request to edit the data made by a client, and a notifying module for, upon the updating the shared state, notifying another client of the updated state.