Showing papers on "System bus published in 2011"

Bus Selection in Multibus DC Microgrids

Abstract: DC power systems can be made more reliable by using multiple buses for redundancy. Multiple buses provide multiple configuration options for supplying power to the load. Diode OR'ing with auctioneering diodes is perhaps the most common method to connect a load to multiple buses. Although the diode action is automatic and fault-tolerant, it results in ill-defined bus currents when the bus voltages are similar and the potential for uncontrolled switching in a faulted high-impedance system-operating scenarios not often included in a discussion on auctioneering diodes. Active switching and bus converters with auctioneering diodes are control techniques that overcome these limitations by providing full control over the bus selection process. Using local information in the form of the bus voltage, these techniques do not rely on a centralized controller, which improves system reliability. Dwell time is proposed as a technique to stabilize the state-dependent switching in the bus selector.

Power and pin efficient chip-to-chip communications with common-mode rejection and sso resilience

Abstract: In bus communications methods and apparatus, a first set of physical signals representing the information to be conveyed over the bus is provided, and mapped to a codeword of a spherical code, wherein a codeword is representable as a vector of a plurality of components and the bus uses at least as many signal lines as components of the vector that are used, mapping the codeword to a second set of physical signals, wherein components of the second set of physical signals can have values from a set of component values having at least three distinct values for at least one component, and providing the second set of physical signals for transmission over the data bus in a physical form.

Error control coding for orthogonal differential vector signaling

Abstract: Using a transformation based, at least in part, on a non-simple orthogonal matrix, data may be transmitted over a data bus in a manner that is resilient to one or more types of signal noise, that does not require a common reference at the transmission and acquisition points, and/or that has a pin-efficiency that is greater than 50% and may approach that of single-ended signaling. Such transformations may be implemented in hardware in an efficient manner. The transformation may be combined with methods from forward error correction to lower the required transmission power.

Methods and systems to accomplish variable width data input

Abstract: Disclosed are methods and systems for variable width data input to a pattern-recognition processor. A variable width data input method may include receiving bytes over a data bus having a first width and receiving one or more signals indicating the validity of each of the one or more bytes. The valid bytes may be sequentially provided to a pattern-recognition processor in an 8-bit wide data stream. In an embodiment, a system may include one or more address lines configured to provide the one or more signals indicating the validity of the bytes transferred over the data bus. The system may include a buffer and control logic to sequentially process the valid bytes.

Portable articulated arm coordinate measuring machine with multi-bus arm technology

Abstract: A portable articulated arm coordinate measuring machine (AACMM) with multi-bus arm technology that includes a manually positionable articulated arm portion, a measurement device, and an electronic circuit The electronic circuit is configured to receive a position signal from the arm portion and to provide data corresponding to a position of the measurement device The AACMM further includes a probe end, an accessory device, an encoder data bus, and a first device data bus The encoder data bus is coupled to the arm portion and the electronic circuit, and the encoder data bus is configured to send the position signal to the electronic circuit The first device data bus is coupled to the accessory device and the electronic circuit The first device data bus is configured to operate simultaneously with and independently of the encoder data bus for sending accessory device data from the accessory device to the electronic circuit

Implementation and Testing of Directional Comparison Bus Protection Based on IEC61850 Process Bus

Abstract: A directional comparison bus protection unit (DCBPU) can provide a high speed bus fault clearing in the IEC61850 process-bus environment. This technique is based on superimposed fault direction for each circuit connected to the protected bus. In this paper, the implementation and testing of a superimposed directional comparison technique for bus protection based on an IEC61850 process bus is investigated. Design, hardware implementation, and related issues of DCBPU are described. A unique test setup is proposed and developed for testing DCBPU, including merging unit simulator, traffic generator, prototype DCBPU, and Ethernet switches to simulate the real IEC 61850-based substation automation process bus. Test results are reported.

1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing

Abstract: Aiming to resolve memory bottlenecks in multi-core system, novel 1-Tbyte/s 1-Gbit DRAM architecture based on a multi-core configuration and 3-D interconnects was developed. The DRAM stacked on a multi-core CPU has 512-bit I/Os with through-silicon-via (TSV) distributed in 16 memory cores. Five-stage pipelined architecture in the compact DRAM core was developed to reduce the operation cycle of the data-bus to 2 ns. A low-noise early-bar-write scheme for an 8-ns cycle array operation and 16-Gbit/s I/O circuits on TSV were also developed. The proposed DRAM architecture greatly improves power efficiency. TSV scheme reduces the parasitic capacitance of the interconnects between the DRAM and CPU, and multi-core architecture reduces the length of the data bus on the DRAM. A 1-Gbit DRAM was designed based on the 45-nm stand-alone DRAM process. Chip size is 51.6 mm 2 assuming 4F 2 memory cells, and the density is about 5 times higher than that of embedded DRAM. Circuit simulations confirmed the 2-ns operation of the data bus, 8-ns operation of the memory array, and 16-Gbit/s operation of I/O circuits. Power consumption is 19.5 W, providing power efficiency of 51.3 Gbyte/s/W, which is an order of magnitude higher than that of conventional DRAMs.

1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing

Abstract: Aiming to resolve memory bottlenecks in multi-core system, novel 1-Tbyte/s 1-Gbit DRAM architecture based on a multi-core configuration and 3-D interconnects was developed. The DRAM stacked on a multi-core CPU has 512-bit I/Os with through-silicon-via (TSV) distributed in 16 memory cores. Five-stage pipelined architecture in the compact DRAM core was developed to reduce the operation cycle of the data-bus to 2 ns. A low-noise early-bar-write scheme for an 8-ns cycle array operation and 16-Gbit/s I/O circuits on TSV were also developed. The proposed DRAM architecture greatly improves power efficiency. TSV scheme reduces the parasitic capacitance of the interconnects between the DRAM and CPU, and multi-core architecture reduces the length of the data bus on the DRAM. A 1-Gbit DRAM was designed based on the 45-nm stand-alone DRAM process. Chip size is 51.6 mm2 assuming 4F2 memory cells, and the density is about 5 times higher than that of embedded DRAM. Circuit simulations confirmed the 2-ns operation of the data bus, 8-ns operation of the memory array, and 16-Gbit/s operation of I/O circuits. Power consumption is 19.5 W, providing power efficiency of 51.3 Gbyte/s/W, which is an order of magnitude higher than that of conventional DRAMs.

Automotive diagnostic data monitoring systems and methods

Abstract: Embodiments of the present invention are generally directed to automotive diagnostic data monitoring systems and methods. An exemplary embodiment of the present invention provides an automotive diagnostic data monitoring system comprising an automotive transceiver integrated with a vehicle diagnostics data bus, a first local transceiver, and a gateway connected to a wide area network. The automotive transceiver can be configured to transmit and receive information to and from the first local transceiver. The first local transceiver can be configured to transmit and receive information to and from the gateway. The automotive transceiver can be located about an automobile. The vehicle diagnostic data bus can contain diagnostic information related to an automobile. Other aspects, features, and embodiments are also claimed and described.

System and method for optimizing interconnections of components in a multichip memory module

Abstract: An apparatus and method couples memory devices in a memory module to a memory hub on the module such that signals traveling from the hub to the devices have approximately the same propagation time regardless of which device is involved. Specifically, the devices are arranged around the hub in pairs, with each pair of devices being oriented such that a functional group of signals for each device in the pair, such as the data bus signals, are positioned adjacent each other on a circuit board of the module. This allows for a data and control-address busses having approximately the same electrical characteristics to be routed between the hub and each of the devices. This physical arrangement of devices allows high speed operation of the module. In one example, the hub is located in the center of the module and eight devices, four pairs, are positioned around the hub.

Content addressable memory (cam)

Abstract: A non-volatile Content Addressable Memory element including a non volatile memristor memory element; a data bus for applying a data signal to be programmed into the memristor memory element; a search bus for applying a search term; an output or match bus; logic to selectively enable the search bus and the data bus; wherein the logic is configurable to set the logic state of the memristor according to a logic signal applied to the data bus, and configurable to enable the logic state of the memristor to be compared to a logic state on the search bus with the match bus signaling a true logic state upon matching.

System-wide energy optimization for multiple DVS components and real-time tasks

Abstract: Most dynamic voltage and frequency scaling (DVS) techniques adjust only CPU parameters; however, recent embedded systems provide multiple adjustable clocks which can be independently tuned. When considering multiple components, energy optimal frequencies depend on task set characteristics such as the number of CPU and memory access cycles. In this work, we propose a realistic energy model considering multiple components with individually adjustable frequencies such as CPUs, system bus and memory, and related task set characteristics. The model is validated on a real platform and shows less than 2% relative error compared to measured values. Based on the proposed energy model, we present an optimal static frequency assignment scheme for multiple DVS components to schedule a set of periodic real-time tasks. We simulate the energy gain of the proposed scheme compared to other DVS schemes for various task and system configurations, showing up to a 20% energy reduction. We also experimentally verify energy savings of the proposed scheme on a real hardware platform.

Power Adapter Having a Universal Serial Bus Hub

Abstract: A power adaptor for a host device and method of operating the same. In one embodiment, the power adapter includes a power converter (910) and a universal serial bus hub (920). The power adapter also includes an integrated power/ universal serial bus connector (950), coupled to the power converter (910) and the universal serial bus hub (920), configured to provide power to and universal serial bus communication with a host device.

Hardware accelerator module and method for setting up same

Abstract: A hardware accelerator module is driven by a system processor via a system bus to sequentially process data blocks of a data stream as a function of a parameter set defined by the processor. The module includes a register block adapted to receive parameter sets from the system processor, an accelerator core adapted to receive streaming data, to process data blocks of said streaming data in a manner defined by a parameter set, and to output processed streaming data, and a parameter buffering block adapted to consecutively store a plurality of parameter sets and to sequentially provide the parameter sets to the hardware accelerator core as a function of a busy state of the hardware accelerator core. The parameter buffering block enables to reduce downtimes of hardware accelerators, to increase data throughput, and to reduce the risk of a processor overload in a processor which drives several hardware accelerators.

Motion control system

Abstract: The present invention relates to a motion control system (1), having a first motion controller (3), a second motion controller (5), a data bus (11) and the global time, wherein the first motion controller (3) a first data track (15) having a time depends on the global time stamp, and wherein the second motion controller (5) a second data track (17) having a global time depends on the time stamp.

Communication with lighting units over a power bus

Abstract: A first entity communicates with a second entity over a shared power bus by switching the bus to a high-impedance state and modifying the voltage on the power bus, in accordance with an outgoing communication, such that the modified voltage is detected by the second entity and the communication is received thereto.

Method and system for diagnosing a fault or open circuit in a network

Abstract: A fault injection circuit (34) injects a test signal into a data bus (17) with a normal high logic level and a normal low logic level. The test signal has a greater logic level greater than the normal high logic level of the data bus (17) or a lower logic level lower than the normal low logic level of the data bus (17). An analog-to- digital converter (36) is coupled to a voltage level detector (35) for sensing an aggregate level of an aggregate signal on the data bus (17). The aggregate signal is composed of the termination circuit signal and the test signal. A diagnostic tool (10) determines whether a faulty connection between the data bus (17) and a network device (44, 144, 244) exists, where the sensed aggregate level exceeds at least one of the normal high logic level and the normal low logic level.

The HADES DAQ System: Trigger and Readout Board Network

Abstract: HADES is a di-electron spectrometer operating at GSI, Germany. Currently, the HADES data and trigger system is being upgraded. The main aim is to substantially increase the event rate capabilities by a factor of up to 20 to reach 100 kHz in light systems and 20 kHz in heavy ion reactions. The data rate will be about 400 MByte/s in peak. In this context, the complete readout system has been exchanged to use optical communication. In this contribution we present a general-purpose real-time network protocol that has been developed to meet the new requirements. These include strong timing constraints with latencies less than 5 μs for endpoint-to-endpoint communication through up to 10 intermediate hubs in a star-like network setup. In summary, this network connects over 500 FPGAs distributed over the whole HADES detector. Monitoring and slow control features as well as readout and trigger distribution were joined in a single network protocol. Hence, channel multiplexing with inherent arbitration by priority is implemented. Switching between channels takes less than 100 ns. For control and monitoring, a dedicated channel provides a data bus with a virtual address space spanning the whole network. The configuration is highly flexible and thus adaptable to different experimental setups and hardware.

System and method to address and control serially connected LEDs

Abstract: This application relates to the systems and methods for networking and control of lighting systems In particular, this application relates to the addressing and control of light emitting diodes (LEDs) connected serially on a bus within a network of serially bussed LEDs The approaches described in this application simplify and lower the cost of control by distributing the control functions between a serial bus controller and controllers associated with individual LEDs or LED circuits on the serial bus Hardware intensive decoding of predefined addresses, or time consuming address processing and determining algorithms, are not employed Instead, the addressing method disclosed both simplifies the system by reducing hardware requirements and improves the speed of the data packets and reduces packet latency moving down the serial bus

Method and apparatus for effective utilization of energy storage components within a microgid

Abstract: A method for effectively utilizing energy storage components within a microgrid may include the steps of connecting a first plurality of energy storage components to a DC bus through switches, connecting a second plurality of energy storage components to an AC bus through inverters, connecting controllers to the energy storage components, connecting a first plurality of the controllers to the DC bus to regulate bidirectional flow of energy between the DC bus and the first plurality of energy storage components and connecting a second plurality of the controllers to the AC bus to regulate bidirectional flow of energy between the AC bus and the second plurality of energy storage components. The controllers may be interconnected with a local energy storage system bus and controlled via a master microgrid controller connected to the local energy storage system bus. The controllers may have a state of charge and a state of health algorithm adapted to measure the state of charge and the state of health of the energy storage components under dynamic charge or discharge conditions.

Reducing simultaneous switching outputs using data bus inversion signaling

Abstract: An apparatus includes a plurality of data lines defining a data bus for communicating data. A controller is operable to communicate a plurality of data transfers over the data bus using a plurality of data time slots, wherein for at least a subset of the data time slots the controller is operable to communicate an associated data bus inversion indicator indicating that bits communicated during the associated data time slot are inverted, the data bus inversion indicators for the subset of the data transfers are grouped into a data bus inversion vector, and the controller is operable to communicate a global data bus inversion indicator indicating an inversion of the data bus inversion vector.

Application proxy-based network management system isolation control device

Abstract: The invention provides an application proxy-based network management system isolation control device, which comprises an intranet processing unit, an extranet processing unit and a data exchange unit, wherein the intranet processing unit comprises an isolation exchange control module and an application proxy module; the extranet processing unit comprises an isolation exchange control module and an application proxy module; and the data exchange unit consists of a special bus interface and a bus switch and is based on an non-(internet protocol) IP protocol, the special data bus exchanges the data between the intranet processing unit and the extranet processing unit, and prevents attack from the leaks of the transmission control protocol (TCP)/IP. In the invention, the network attack behavior aiming at a TCP stack can be prevented by adopting a specific non-IP protocol and an internal isolation exchange interface.

Design and Implementation of High Performance AHB Reconfigurable Arbiter for Onchip Bus Architecture

Abstract: Resolution is a big issue in SOC (system On Chip) while dealing with number of master trying to sense a single data bus. The effectiveness of a system to resolve this priority resides in its ability to logical assignment of the chance to transmit data width of the data, response to the interrupts etc. The purpose of this paper is to propose the scheme to implement reconfigurable architecture so that it can be interface with any common IP core of such a system using the specification of AMBA bus protocol. The scheme involves the typical AMBA features of 'single clock edge transition ', Split transaction ','several bus masters ', 'burst transfer '.The bus arbiter ensures that only one bus master at a time is allowed to initiate data transfers. Here we have proposed and implemented the reconfigurable arbitration algorithm, such as highest priority or fair access and round robin can be implemented depending on the application requirements. The design architecture is written using VHDL(Very High Speed Integrated Circuits Hardware Description Language) code using Xilinx ISE Tools. The architecture is modeled and synthesized using RTL(Register Transfer Level) abstraction and Implemented on Virtex2 series.

Smart home monitoring system based on wireless fidelity (WIFI) and hyper text transport protocol (http) technologies and running method thereof

Abstract: The invention discloses a smart home monitoring system based on wireless fidelity (WIFI) and hyper text transport protocol (http) technologies and a running method thereof The system comprises a master controller, and a remote operation terminal, a local operation terminal a power control part and a regulation and control monitoring part which are connected with the master controller by an RS485 data bus The running method for the system comprises the processes of hardware management, task designing, plan designing, rule designing, holiday setting, task execution, task queue management, hardware condition management and the like The system can be operated and monitored by a local terminal, a remote phone mobile, a remote personal digital assistant (PDA) or a remote computer, and is low in using cost, simply structured, convenient to install and operate, applicable to the satisfaction of flexible home monitoring needs of various house structures, stable in running, safe and reliable

Distributed Computing Bus

Abstract: A distributed computing bus that provides both data transport and ambient computing power is provided. Contemplated buses comprise a network fabric of interconnected networking infrastructure nodes capable of being programmed before or after installation in the field. A fabric manager organizes the fabric into a bus topology communicatively coupling computing elements that exchange payload data using a bus protocol. Nodes within the bus topology operate on the payload data as the data passes through the node on route to its destination.

Arbitrating bus transactions on a communications bus based on bus device health information and related power management

Abstract: Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices.

Multifunctional Bluetooth earphone

Abstract: The utility model discloses a multifunctional Bluetooth earphone, which comprises an earphone body, a Bluetooth chip, an MP3 (moving picture experts group audio layer-3) processor, an operating key, a hot plug bone conduction microphone, a speaker, and an antenna, wherein the Bluetooth chip is connected with the antenna through an external radio frequency element; and the multifunctional Bluetooth earphone also comprises an FM (frequency modulation) chip, a USB (universal series bus) interface, and a TF (TransFLash) card slot. The MP3 processor is connected with the Bluetooth chip and the FM chip through an I2C (inter-integrated circuit) bus, and is connected with a FLASH memory and an LED (light-emitting diode) through an address/data bus; and the MP3 processor, the Bluetooth chip, and the FM chip are electrically connected with the microphone and the speaker through a voice coding-decoding circuit and an audio frequency processing circuit. The multifunctional Bluetooth earphone realizes perfect combination between the Bluetooth earphone, the MP3 processor, an FM radio, the bone conduction microphone, a phone recorder, the TF card slot, and the USB interface, integrates a plurality of functions together, can automatically switch to corresponding function modules to work, is more convenient to use, and is convenient to carry and store.

Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program product

Abstract: Various systems, apparatuses, processes, and programs may be used to calculate a multiply-sum of two carry-less multiplications of two input operands. In particular implementations, a system, apparatus, process, and program may include the ability to use input data busses for the input operands and an output data bus for an overall calculation result, each bus including a width of 2n bits, where n is an integer greater than one. The system, apparatus, process, and program may also calculate the carry-less multiplications of the two input operands for a lower level of a hierarchical structure and calculating the at least one multiply-sum and at least one intermediate multiply-sum for a higher level of the structure based on the carry-less multiplications of the lower level. A certain number of multiply-sums may be output as an overall calculation result dependent on mode of operation using the full width of said output data bus.

Multiprocessor computer system having a plurality of working processors and a plurality of monitoring processors for monitoring the working processors

Abstract: The invention relates to a multiprocessor computer system (1) having a plurality of working processors (7), which are set up to execute a user program, and a plurality of monitoring processors (8, 9) for monitoring the working processors (7), having the following features: a) the monitoring processors (8, 9) are connected to one another via a data bus (11) for the purpose of interchanging data with one another, b) one monitoring processor is in the form of a master monitoring processor (9) and the remaining monitoring processors are in the form of slave monitoring processors (8), c) one slave monitoring processor (8) is respectively associated with one or more working processors (7) and is set up to record operating data relating to this or these operating processor(s) (7), d) the master monitoring processor (9) has a communication interface (5) for interchanging data with devices (26) outside the multiprocessor computer system (1), which communication interface is separate from the data bus (11), e) the master monitoring processor (9) is set up to collect operating data relating to the working processors (7), as recorded by the slave monitoring processors (8), to evaluate said data and to check the latter for compliance with at least one predetermined communication criterion, and to transmit operating data relating to the working processors (7), as collected by the slave monitoring processors (8), directly or in a preprocessed form via the communication interface (5) when the communication criterion is complied with.

Using SDRAMs for two-dimensional accesses of long 2 n × 2 m -point FFTs and transposing

Abstract: When transposing large matrices using SDRAM memories, typically a control overhead significantly reduces the data throughput. In this paper, a new address mapping scheme is introduced, taking advantage of multiple banks and burst capabilities of modern SDRAMs. Other address mapping strategies minimize the total number of SDRAM page-opens while traversing the two-dimensional index-space in row or column direction. The new approach uses bank interleaving methods to hide wait cycles, caused by page-opens. In this way, data bus wait cycles do not depend on the overall number of page-opens directly. It is shown, that the data bus utilization can be increased significantly, in particular, if memories are accessed with parallel samples. Therefore, double buffering can be omitted. As a special operation, 2D-FFT processing for radar applications is considered. Depending on SDRAM parameters and dimensions, a continuous bandwidth utilization of 96 to 98% is achieved for accesses in both matrix directions, including all refresh commands.