Showing papers on "Transistor published in 1972"

Development, Operation, and Application of the Ion-Sensitive Field-Effect Transistor as a Tool for Electrophysiology

Abstract: A new solid-state device has been developed for the measurement of ion activities in electrochemical and biological environments. One can recognize in the device the properties of both a glass electrode and a field-effect transistor. This justifies the name ion-sensitive field-effect transistor. The device makes it possible to measure ion activities without using a reference electrode. For its application, a special electronic circuit is described. Results of measured Na + and H + ion activities are given in detail. As an example for electrophysiological application, results are shown of recorded extracellular ion pulses measured with a guinea pig taenia coli.

Ion-implanted complementary MOS transistors in low-voltage circuits

Abstract: Simple but reasonably accurate equations are derived which describe MOS transistor operation in the weak inversion region near turn-on. These equations are used to find the transfer characteristics of complementary MOS inverters. The smallest supply voltage at which these circuits will function is approximately 8kT/q. A boron ion implantation is used for adjusting MOST turn-on voltage for low-voltage circuits.

Electron dynamics in short channel field-effect transistors

Abstract: The dynamics of electrons between the source and drain of a microwave field-effect transistor (FET) have been studied using a Monte Carlo method. The spatial dependence as well as the time dependence of the average electron velocity is presented. It is shown that in silicon the relaxation time is short enough not to influence the figure of merit of the transistor. However, in direct gap polar semiconductors (e.g., GaAs), the electrons can have a velocity well above their saturation value for an appreciable length of time and, consequently, over a distance nonnegligible compared to the length of the active region of a high frequency FET. This could improve the figure of merit of the FET.

Fundamental limitations in microelectronics—I. MOS technology

Abstract: The physical phenomena which will ultimately limit MOS circuit miniaturization are considered. It is found that the minimum MOS transistor size is determined by gate oxide breakdown and drain-source punch-through. Other factors which limit device size are drain-substrate breakdown, drain ‘corner’ breakdown and substrate doping fluctuations. However these limitations are less severe than the oxide breakdown limitation mentioned above. Power dissipation and metal migration limit the frequency and/or packing density of fully dynamic and of complementary MOS circuits. In static non-complementary circuits, power dissipation is the principal limitation of the number of circuit functions per chip. The channel length of a minimum size MOS transistor is a factor of 10 smaller than that of the smallest present day devices. The tolerances required to manufacture such a transistor are compatible with electron beam masking techniques. It is thus possible to envision fully dynamic silicon chips with up to 10^7–10^8 MOS transistors per cm^2.

Merged-transistor logic (MTL)-a low-cost bipolar logic concept

Abstract: The authors describe a novel bipolar logic featuring a direct injection of minority carriers into the switching transistor. MTL is based on inverters having decoupled multicollector outputs for the logical combinations. The devices are self-isolated and no ohmic load resistors are required. This is a key to monolithic logic chips of very high functional density and low power dissipation. On experimental chips an excellent power-delay product of 0.35 pJ has been measured. These experiments show that a density of 100 gates/mm/SUP 2/ can be achieved with present manufacturing tolerances (minimum dimensions: 0.3-mil metal line width, 0.15-mil spacing, 0.2/spl times/0.2-mil/SUP 2/ contact holes).

D-MOS transistor for microwave applications

Abstract: A new n-channel silicon MOS transistor is described that can be fabricated with channel lengths of less than 1 µ by using a double-diffusion process similar to that used in bipolar transistor fabrication. The dimensional tolerances are not tighter than those used in the processing of conventional MOS transistors. This device (called D-MOST) shows gain in the GHz range and a noise figure comparable to that of microwave transistors. The f max is 10 GHz and the noise figure is 4.0 dB at 1 GHz. A brief theory of the D-MOST is followed by the design considerations for a discrete microwave device. Results from s-parameter measurements in the range of 0.1-2.5 GHz are presented along with graphs showing the gains and the stability factor. A simple equivalent circuit is derived from the measurements. Applications of the D-MOST are described.

Steady-state junction temperatures of semiconductor chips

Abstract: The temperature drop between a transistor junction and the base of a silicon chip is dependent upon the power to be dissipated as well as the geometry of the device. This problem in three-dimensional heat conduction is analytically solved for boundary conditions which approximate a set of operating conditions. Nondimensional curves and examples summarizing typical solutions have been included to illustrate problem solving techniques.

GaAsGaAlAs heterojunction transistor for high frequency operation

Abstract: A bipolar transistor structure is proposed having application for either high frequency operation or integration with certain types of light emitting devices. The structure involves liquid phase epitaxially grown layers of GaAs for the collector and base regions, and of Ga1−xAlxAs for the heterojunction emitter. The high frequency potential of this device results primarily from the high electron mobility in GaAs and the ability to heavily dope the base region with slowly diffusing acceptors. The Ga1−xAlxAs emitter region provides a favorable injection efficiency and, because it is etched preferentially relative to GaAs, access to the base layer for making contact. Transistor action with d.c. common emitter current gains of 25 have been thus for observed. Calculations of the high speed capability of this transistor are presented.

Schottky barrier type field effect transistor

Abstract: A Schottky barrier gate field effect transistor is capable of operating in the enhancement mode. The transistor includes a gallium arsenide layer formed on a substrate. The relationship between the thickness W and impurity concentration N of the gallium arsenide layer is given by the expression: 2 X 103CM 1/2 < W . square root N < 3 X 103 cm 1/2.

Principles of electronic instrumentation

Abstract: Direct Current Circuits. Capacitors and Inductors. Alternating Current Circuits I. Alternating Current Circuits II. Diodes and Some Applications. Test Equipment and Measurement. Transducers. Transistors. Operational Amplifiers. Waveform Generators. Digital Basics. Digital Circuitry. Microprocessor Basics. Digital and Analog I/O. Noise.

Characterization and measurement of the base and emitter resistances of bipolar transistors

Abstract: Most previously published methods of measuring transistor base resistance are surveyed and compared. The input impedance circle diagram method is examined in detail and correction factors due to parasitic capacitances are derived. Emitter series resistance is also estimated from this data. A new method of measuring base resistance requiring much less measurement effort is introduced and shown to give good agreement with the circle diagram method. This method is called the phase cancellation method and gives an estimate of base resistance from the common base input impedance at the collector current where its imaginary part is zero. Also an estimate of series emitter resistance is obtained from this measurement and shown to agree well with other methods.

Measurement of emitter and collector series resistances

Abstract: Emitter and collector series (extrinsic) resistances can be evaluated by measuring the open-circuited (floating) junction voltage as the other junction is forward biased. Evaluation can be carried out on either a point-by-point basis or with the aid of a curve tracer. Specific results are indicated for a 2N4400 transistor and an experimental transistor.

Limitations in microelectronics — II. Bipolar technology☆

Abstract: The physical phenomena which will ultimately limit miniaturization of planar bipolar integrated circuits are examined. The maximum packing density is obtained by minimizing the supply voltage and the size of the devices. The minimum transistor size is determined by junction breakdown, punch through and doping fluctuations. For circuits that are fully active the maximum number of circuit functions per chip is determined by power dissipation. The packing density of read-only memories becomes limited by the area occupied by devices and interconnections. The limitations of MOS and bipolar technologies are compared. It is concluded that read-only memories will reach approximately the same performance and packing density with MOS and bipolar technologies, while fully active circuits will reach the highest levels of integration with dynamic MOS or complementary MOS technologies.

Input transient protection for complementary insulated gate field effect transistor integrated circuit device

Abstract: A COS/MOS INTERGRATED CIRCUIT DERIVE OF THE TYPE HAVING A DIFFUSED WELL REGION AND COMPLEMENTARY INSULATED GATE FIELD EFFECT TRANSISTORS INSIDE AND OUTSIDE THE WELL REGIONS, RESPECTIVELY, HAS AN INTEGRAL CIRCUIT FOR PROTECTING THE GATE INSULATORS OF THE INSULATED GATE FIELD EFFECT TRANSISTORS FROM DESTRUCTIVE TRANSIENTS. THE PROTECTION CIRCUIT INCLUDES A DIFFUSED RESISTOR MADE AT THE SAME TIME AS THE SOURCE AND DRAIN REGIONS OF THE TRANSISTOR WHICH IS WITHIN THE WELL REGION. THE DIFFUSED RESISTOR IS DISPOSED WITHIN A REGION MADE AT THE SAME TIME AS THE WELL REGION.

Silicon-gate CMOS frequency divider for electronic wrist watch

Abstract: An integrated complementary MOS transistor scale-of-two counter for applications in electronic wrist watches has been realized. Silicon-gate technology applied to a very simple but safe dividing circuit has resulted in a substantial reduction of the total area of the integrated structure with the following performance. At a supply voltage of 1.35 V the maximum frequency is 2 MHz and the dynamic power consumption per stage is 1.6 nW/kHz. The complementary substrate is obtained by a sealed-capsule low-surface concentration diffusion and doped oxides as impurity sources are used to allow simultaneous diffusion of both types of MOS transistors. A simple dynamic circuit derived from the basic structure is described.

Dc-ac converter

Abstract: A DC-AC transistor converter for supplying a low-pressure mercury vapor discharge lamp A capacitive potential divider is used for operation of the transistor while one of the capacitors of this potential divider is arranged between the emitter and the base of the transistor in the converter

An accurate two-dimensional numerical analysis of the MOS transistor

Abstract: A two dimensional numerical analysis has been made for MOS transistors with both small and large values of channel lenghts and various bias conditions. Results are compared with a simplified analysis of the MOST and with experimental data obtained on devices. Detailed pictures of the free carriers density distribution and of the voltage distribution are presented for various channel lengths and two dimensional effects are clearly seen near the source and the drain that are very hardly accounted for in a simplified one dimensional analysis. Such a program seems to be a very powerful tool for device optimisation and physical understanding of the behaviour of very small devices used in complex circuits.

Threshold shift calculations for ion implanted MOS devices

Abstract: The solutions of Poisson's equation applicable to ion implanted MOS devices have been used to generate capacitance-voltage relationships for capacitors and threshold voltage shifts for transistors. The calculations agree well with previously published transistor data for profiles centered near Si-SiO 2 interface. These shallow implants ( μ m) are easily controlled by the gate and yield voltage shifts equal to that expected for all of the charge lumped at the silicon surface. In addition, the observed saturation of gate voltage shift for deeper implants in enhancement mode transistors can be duplicated by the calculations provided that the stopping power of SiO 2 is reduced as has been proposed elsewhere. Further, it has been predicted that gate control will be lost for depletion mode transistors with sufficiently deep implants. This is caused by the formation of a deep channel which is isolated from gate control by an induced surface charge layer. The inability of the gate field to pinch off the channel defeats device use for transistor inverter loads.

Variable capacitance device

Abstract: This specification discloses variable capacitance devices which vary their capacitances under the influence of DC bias voltages or radiations. One embodiment comprises a PN junction diode, a dielectric thin film deposited on the surface of said junction diode at which the junction terminates and a conducting electrode deposited on the dielectric thin film, in which the area of an equivalent plate electrode formed in said junction diode is varied by changing the thickness of a depletion region. In another embodiment, a nonlinear resistance layer deposited on the dielectric thin film is employed. As a DC voltage as applied to the nonlinear resistance layer is increased, the lateral conductivity of the nonlinear resistance layer increases and the area of the equivalent plate electrode facing the conducting electrode is increased. A further embodiment employs a thin film transistor or a MIS transistor to vary the area of the equivalent plate electrode provided therein.

Methods of forming self aligned transistor structure having polycrystalline contacts

Abstract: Disclosed are three processes, which all employ a common sequence of steps, for forming discrete and integrtated circuit transistors having emitters self-aligned between base enhancements and various polycrystalline silicon contacting members. The first process forms transistors having polycrystalline emitter contacts. The second process employs anisotropic etching techniques for forming self-aligned, integrated circuit transistors having polycrystalline emitter and collector contacts along with shallow isolation and collector buried layer contacting diffusions. The third process provides a transistor having polycrystalline silicon contacts to the emitter and base enhancement regions and utilizes boron doped polycrystalline silicon base contacts as an etch stop.

Compatible pnp and npn devices in an integrated circuit

Abstract: Compatible, matched, complementary semiconductor devices are fabricated in a common semiconductor body using a combination of oxide-masked diffusion, epitaxial deposition and photoresist-masked, ion implantation. A pair of zones of opposite conductivity type are formed in a high resistivity substrate by sequential oxide-masked diffusion, ion implantation, epitaxial deposition and subsequent out-diffusion. Using a series of photoresist masks, successive ion-implantation steps of P- and N-type impurities produce the base and emitter zones of the complementary transistors as well as zones of enhanced conductivity for connecting to the collector zone.

Field effect transistor structures and methods

Abstract: A field effect transistor is made in a mesa configuration with the top portion of the mesa being the source region and with the limits of the gate electrode being defined by a shadow mask that overhangs part of the mesa. A drift region layer of moderately high resistivity is included between the transistor channel region and the drain region and constitutes the upper wafer substrate surface from which the mesa extends. A thin implanted layer in the upper surface of the drift region layer limits the extent of the channel in the mesa, and a thick oxide over the drift layer reduces the coupling from the gate electrode to the drift region.

Semiconductor memory having single transistor storage elements and a flip-flop circuit for the evaluation and regeneration of information

Abstract: A dynamic semiconductor memory having a plurality of single transistor storage elements connected to a digit line and respective selection lines, an evaluation and regeneration circuit including a flip-flop having a pair of input/output points, each of the points connected to one of the digit lines, and means connecting the points including a controllable semiconductor switch operable to place the points at equal potentials prior to reading from a selected storage element.

Precision switching circuit for analog signals

Abstract: A precision high-speed, low impedance switching circuit is disclosed which is suitable for use with video or other high frequency analog signals. A J-FET is used as the switching element but is controlled by means of a novel circuit which minimizes channel impedance modulation effects. The gate of the J-FET is connected to the output of a control transistor, the input of the control transistor being connected to the input signal, thereby allowing the effective parasitic input capacity at the gate of the J-FET switch to be charged and discharged in accordance with the fluctuations of the input signal.

Industry Update

Abstract: Designers of microprogrammed computers have been using solid-state, random-access memories as scratch- pads and solid-state read-only memo- ries to store microinstructions and program constants. TTL (transistor- transistor logic) integrated circuits are frequently chosen because TTL speed is high.

Vertical channel junction field-effect transistors and method of manufacture

Abstract: The disclosed junction field-effect transistor (FET) has a precisely controlled gate configuration which enables either high power operation or high frequency operation or both. The FET is manufactured by steps including the growing of a first epitaxial layer having a predetermined crystallographic orientation on a substrate to form a drain. Next, a first anisotropic etch of the epitaxial layer provides "U"-shaped grooves with flat bottoms, therein through which a gate is diffused having internal side walls of uniform depth that define the source-to-drain channel. A second epitaxial layer is then grown on the surface of the first epitaxial layer and of the gate to provide a source. A second anisotropic etch exposes a portion of the gate, which also forms an etch stop, to facilitate electrical contact thereto. Current flowing through the channel is controlled in response to an input signal applied between the gate and source which adjusts the thickness of a depletion region extending into the channel.

Gyrator employing field effect transistors

Abstract: A gyrator circuit of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180* phase reversal. All active elements are MOS field effect transistors. Each amplifier comprises a differential amplifier configuration with current limiting transistor, followed by an output transistor in cascode configuration, and two load transistors of opposite conductivity type from the other transistors. A voltage divider control circuit comprises a series string of transistors with a central, voltage input to provide control, with locations on the amplifiers receiving reference voltages by connection to appropriate points on the divider. The circuit produces excellent response and is well suited for fabrication by integrated circuits.

DC / AC converter

Abstract: A DC-AC converter includes a transformer with its primary winding in series with a transistor across the terminals of a DC voltage source. A resistor is connected between the emitter and base of the transistor and a coupling capacitor connects a coupling winding of the transformer to the base of the transistor. An auxiliary DC voltage source is included in the connection between the emitter and the resistor so that the converter is less sensitive to variations in the DC source voltage.

Analog transmission gate

Abstract: A transistor switching network, responding to a logic input, switches current selectively into one of a number of nodes, each node connecting a pair of bipolar transistors coupled differentially in a unity gain amplifier circuit. From a number of analog input signals applied to the differentially connected transistor pairs, only the one coupled to the selected node will produce an output from the voltage follower circuit. Conversely, a single analog input signal may be gated selectively to any one of a number of output terminals.

The GaAs traveling-wave amplifier as a new kind of microwave transistor

Abstract: A versatile solid-state microwave amplifier has evolved from a combination of transistor mechanisms and the transferred-electron effect. The prototype device, called a "traveling-wave transistor," employs a 2-µm layer of n-type GaAs grown epitaxially on a semi-insulating substrate. A transistor-like input launches a traveling space-charge wave that grows exponentially as it moves along the surface to a relatively distant output. There it is converted back into an electromagnetic wave. The long distance between input and output minimizes the feedback capacitance that often limits gain and bandwidth in high-frequency devices. Twelve experimental units show broad-band net gain in X band, with 10-30-dB built-in isolation. One unit exhibits instantaneous net gain from 6.7 to 15.3 GHz; another yields 28 dB at 9.2 GHz. All devices are good for linear microwave signal processing: voltage-controlled phase modulation at constant net gain, or voltage-controlled gain modulation at constant phase. Different bias conditions make possible threshold-sensitive saturated-amplitude amplification of pulses or sinusoids for logic or digital functions.