Showing papers on "VHDL published in 2011"

FPGA-Based Real-Time Emulation of Power Electronic Systems With Detailed Representation of Device Characteristics

Abstract: This paper presents a field-programmable gate array (FPGA)-based real-time digital simulator for power electronic apparatus based on a realistic device-level behavioral model. A three-level 12-pulse voltage source converter (VSC)-fed induction machine drive is implemented on the FPGA. The VSC model is computed at a fixed time step of 12.5 ns, allowing a realistic representation of insulated-gate bipolar transistor (IGBT) nonlinear switching characteristics and power losses. The simulator also models a squirrel-cage induction machine, a direct field-oriented control system, and a pulsewidth modulator to achieve the real-time simulation of the complete drive system. All the models have been implemented using very high speed integrated circuit hardware description language (VHDL). Real-time simulation results have been validated using the measured device-level IGBT characteristics.

Development and Implementation of Parameterized FPGA-Based General Purpose Neural Networks for Online Applications

Abstract: This paper presents the development and implementation of a generalized backpropagation multilayer perceptron (MLP) architecture described in VLSI hardware description language (VHDL). The development of hardware platforms has been complicated by the high hardware cost and quantity of the arithmetic operations required in online artificial neural networks (ANNs), i.e., general purpose ANNs with learning capability. Besides, there remains a dearth of hardware platforms for design space exploration, fast prototyping, and testing of these networks. Our general purpose architecture seeks to fill that gap and at the same time serve as a tool to gain a better understanding of issues unique to ANNs implemented in hardware, particularly using field programmable gate array (FPGA). The challenge is thus to find an architecture that minimizes hardware costs, while maximizing performance, accuracy, and parameterization. This work describes a platform that offers a high degree of parameterization, while maintaining generalized network design with performance comparable to other hardware-based MLP implementations. Application of the hardware implementation of ANN with backpropagation learning algorithm for a realistic application is also presented.

Design and Simulation of UART Serial Communication Module Based on VHDL

Abstract: UART (Universal Asynchronous Receiver Transmitter) is a kind of serial communication protocol; mostly used for short-distance, low speed, low-cost data exchange between computer and peripherals. During the actual industrial production, sometimes we do not need the full functionality of UART, but simply integrate its core part. UART includes three kernel modules which are the baud rate generator, receiver and transmitter. The UART implemented with VHDL language can be integrated into the FPGA to achieve compact, stable and reliable data transmission. It's significant for the design of SOC. The simulation results with Quartus II are completely consistent with the UART protocol.

Design of FPGA-based Sliding Mode Controller for Robot Manipulator.

Abstract: One of the most active research areas in the field of robotics is robot manipulators control, because these systems are multi-input multi-output (MIMO), nonlinear, and uncertainty. At present, robot manipulators is used in unknown and unstructured situation and caused to provide complicated systems, consequently strong mathematical tools are used in new control methodologies to design nonlinear robust controller with satisfactory performance (e.g., minimum error, good trajectory, disturbance rejection). Robotic systems controlling is vital due to the wide range of application. Obviously stability and robustness are the most minimum requirements in control systems; even though the proof of stability and robustness is more important especially in the case of nonlinear systems. One of the best nonlinear robust controllers which can be used in uncertainty nonlinear systems is sliding mode controller (SMC). Chattering phenomenon is the most important challenge in this controller. Most of nonlinear controllers need real time mobility operation; one of the most important devices which can be used to solve this challenge is Field Programmable Gate Array (FPGA). FPGA can be used to design a controller in a single chip Integrated Circuit (IC). In this research the SMC is designed using VHDL language for implementation on FPGA device (XA3S1600E-Spartan-3E), with minimum chattering and high processing speed (63.29 MHz).

An efficient implementation of floating point multiplier

Abstract: In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA. VHDL is used to implement a technology-independent pipelined design. The multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MAC) unit. With latency of three clock cycles the design achieves 301 MFLOPs. The multiplier was verified against Xilinx floating point multiplier core.

A hybrid intelligent controller for a twin rotor MIMO system and its hardware implementation.

Abstract: This paper presents a fuzzy PID control scheme with a real-valued genetic algorithm (RGA) to a setpoint control problem. The objective of this paper is to control a twin rotor MIMO system (TRMS) to move quickly and accurately to the desired attitudes, both the pitch angle and the azimuth angle in a cross-coupled condition. A fuzzy compensator is applied to the PID controller. The proposed control structure includes four PID controllers with independent inputs in 2-DOF. In order to reduce total error and control energy, all parameters of the controller are obtained by a RGA with the system performance index as a fitness function. The system performance index utilized the integral of time multiplied by the square error criterion (ITSE) to build a suitable fitness function in the RGA. A new method for RGA to solve more than 10 parameters in the control scheme is investigated. For real-time control, Xilinx Spartan II SP200 FPGA (Field Programmable Gate Array) is employed to construct a hardware-in-the-loop system through writing VHDL on this FPGA.

FPGA Implementation of an Adaptive Filter Robust to Impulsive Noise: Two Approaches

Abstract: Adaptive filters are used in a wide range of applications such as echo cancellation, noise cancellation, system identification, and prediction. Its hardware implementation becomes essential in many cases where real-time execution is needed. However, impulsive noise affects the proper operation of the filter and the adaptation process. This noise is one of the most damaging types of signal distortion, not always considered when implementing algorithms, particularly in specific hardware platforms. Field-programmable gate arrays (FPGAs) are used widely for real-time applications where timing requirements are strict. Nowadays, two main design processes can be followed for embedded system design, namely, a hardware description language (e.g., VHDL) and a high-level synthesis design tool. This paper proposes the FPGA implementation of an adaptive algorithm that is robust to impulsive noise using these two approaches. Final comparison results are provided in order to test accuracy, performance, and logic occupation.

FPGA implementation of AES algorithm

Abstract: The Advanced Encryption Standard can be programmed in software or built with pure hardware. However Field Programmable Gate Arrays (FPGAs) offer a quicker, more customizable solution. This research investigates the AES algorithm with regard to FPGA and the Very High Speed Integrated Circuit Hardware Description language (VHDL). Software is used for simulation and optimization of the synthesizable VHDL code. All the transformations of both Encryptions and Decryption are simulated using an iterative design approach in order to minimize the hardware consumption.

Random number generation based on digital differential chaos

Abstract: In this paper, we present a fully digital differential chaos based random number generator. The output of the digital circuit is proved to be chaotic by calculating the output time series maximum Lyapunov exponent. We introduce a new post processing technique to improve the distribution and statistical properties of the generated data. The post-processed output passes the NIST Sp. 800-22 statistical tests. The system is written in Verilog VHDL and realized on Xilinx Virtex® FPGA. The generator can fit into a very small area and have a maximum throughput of 2.1 Gb/s.

Novel Sliding Mode Controller for robot manipulator using FPGA.

Abstract: One of the most active research areas in the field of robotics is robot manipulators control, because these systems are multi-input multi-output (MIMO), nonlinear, and uncertainty. At present, robot manipulators is used in unknown and unstructured situation and caused to provide complicated systems, consequently strong mathematical tools are used in new control methodologies to design nonlinear robust controller(s) with satisfactory performance (e.g., minimum error, good trajectory, (and) disturbance rejection). Robotic systems controlling is vital due to the wide range of application(s). Obviously, stability and robustness are the most minimum requirements in control systems; even though the proof of stability and robustness is more important especially in the case of nonlinear systems. One of the best nonlinear robust controllers which can be used in uncertainty nonlinear systems is sliding mode controller (SMC). Chattering phenomenon is the most important challenge in this controller. Most of nonlinear controllers need real time mobility operation; one of the most important devices which can be used to solve this challenge is Field Programmable Gate Array (FPGA). FPGA can be used to design a controller in a single chip Integrated Circuit (IC). In this research the SMC is designed using VHDL language for implementation on FPGA device (XA3S1600E-Spartan-3E), with minimum chattering and high processing speed (63.29 MHz).

A new approach to realize UART

Abstract: In order to connect DSP which has synchronous serial ports to the devices implementing asynchronous communications protocol, a method to implement UART communications based on programmable logic device is proposed in the paper. In the proposed method, the core function of UART is integrated in CPLD with VHDL. Firstly, UART data frame format and operational principle of UART were introduced after reviewing some methods to realize UART. The methods to implement UART transmitter, UART receiver and baudrate generator using VHDL were illustrated in detail. Then pre-simulation and synthesize of VHDL program were executed. Finally, the test with bit error rate was carried out on physical system. Experimental results indicate that 75 percent of the GLB are used by UART, and the bit error rate is less than 10−9. The experiment was implemented utilizing the RS-422 protocol and the baudrate is 62.5kb/s. The proposed method can satisfy the system requirements of high integration, stabilization, low bit error rate, strong anti-jamming and low cost.

AES-512: 512-bit Advanced Encryption Standard algorithm design and evaluation

Abstract: This paper presents an FPGA architecture for a new version of the Advanced Encryption Standard (AES) algorithm. The efficient hardware that implements the algorithm is also proposed. The new algorithm (AES-512) uses input block size and key size of 512-bits which makes it more resistant to cryptanalysis with tolerated area increase. AES-512 will be suitable for applications with high security and throughput requirements and with less chip area constrains such as multimedia and satellite communication systems. An FPGA architectural for AES-512 was developed using VHDL, and synthesized using Virtix-6 and Virtex-7 chips. AES-512 show tremendous throughput increase of 230% when compared with the implementation of the original AES-128.

Digital Parameterizable VHDL Module for Multilevel Multiphase Space Vector PWM

Abstract: The multilevel multiphase technology combines the benefits of multilevel converters and multiphase machines. Recently, a new multilevel multiphase space vector pulsewidth modulation algorithm that is valid for any number of levels and phases was developed. In this paper, a generic digital VHDL module for such an algorithm is presented. This module is parameterizable in relation to the number of levels, the number of phases, and the number of bits of fractional part of the reference vector. It is also technology independent, reusable, and modular. This circuit has been tested by implementation in a field-programmable gate array, with the goal of a balance of speed and area optimization. It was tested by using a five-level five-phase inverter feeding an induction motor.

Simulation of Image Encryption using AES Algorithm

Abstract: With the fast progression of data exchange in electronic way, information security is becoming more important in data storage and transmission. Because of widely using images in industrial process, it is important to protect the confidential image data from unauthorized access.This paper presents the design of a 128 bit encoder using AES Rijndael Algorithm for image encryption. The AES algorithm defined by the National Institute of Standard and Technology(NIST) of United States has been widely accepted. Optimized and Synthesizable VHDL code is developed for the implementation of 128- bit data encryption and process. Xilinx ISE9.2i software is used for synthesis.Timing simulation is performed to verify the functionality of the designed circuit.

An integrated high-level hardware/software partitioning methodology

Abstract: Embedded systems are widely used in many sophisticated applications. To speed the time-to-market cycle, the hardware and software co-design has become one of the main methodologies in modern embedded systems. The most important challenge in the embedded system design is partitioning; i.e. deciding which modules of the system should be implemented in hardware and which ones in software. Finding an optimal partition is hard because of the large number and different characteristics of the modules that have to be considered. In this article, we develop a new high-level hardware/software partitioning methodology. Two novel features characterize this methodology. Firstly, the Particle Swarm Optimization (PSO) technique is introduced to the Hardware/Software partitioning field. Secondly, the hardware is modeled using two extreme implementations that bound different hardware scheduling alternatives. Our methodology further partitions the design into hardware and software modules at the early Control-Data Flow Graph (CDFG) level of the design; thanks to improved modeling techniques using intermediate-granularity functional modules. A new restarting technique is applied to PSO to avoid quick convergence. This technique is called Re-Excited PSO. Our numerical results prove the usefulness of the proposed technique. The target technology is Field Programmable Gate Arrays (FPGAs). We developed FPGA-based estimation techniques to evaluate the costs of implementing the design components. These costs are the area, delay, latency, and power consumption for both the hardware and software implementations. Hardware/software communication is also taken into consideration. The aforementioned methodology is embodied in an integrated CAD tool for hardware/software co-design. This tool accepts behavioral, un-timed, algorithmic-level, VHDL, design representation, and outputs a valid hardware/software partition and schedule for the design subject to a set of area/power/delay constraints. This tool is code named CUPSHOP for (Cairo University PSo-based Hardware/sOftware Partitioning tool). Finally, a JPEG-encoder case study is used to validate and contrast our partitioning methodology against the prior-art methodologies.

An Efficient Implementation of the Non Restoring Square Root Algorithm in Gate Level

Abstract: This paper proposes an efficient strategy to implement modified non restoring algorithm based on FPGA in gate level abstraction of VHDL, which adopt fully pipelined architecture. A new basic building block is called controlled subtract-multiplex (CSM) is introduced. The main principle of the proposed method is similar with conventional non-restoring algorithm, but it only uses subtract operation and append 01, while add operation and append 11 is not used. The proposed strategy has conducted to implement FPGA successfully, and it is offer an efficient in hardware resource.

Neural network training based on FPGA with floating point number format and it’s performance

Abstract: In this paper, two-layered feed forward artificial neural network’s (ANN) training by back propagation and its implementation on FPGA (field programmable gate array) using floating point number format with different bit lengths are remarked based on EX-OR problem. In the study, being suitable with the parallel data-processing specification on ANN’s nature, it is especially ensured to realize ANN training operations parallel over FPGA. On the training, Virtex2vp30 chip of Xilinx FPGA family is used. The network created on FPGA is coded by using VHDL. By comparing the results to available literature, the technique developed here proved to consume less space for the subjected ANN training which has the same structure and bit length, it is shown to have better performance.

Performance Evaluation of Squaring Operation by Vedic Mathematics

Abstract: Highly efficient arithmetic operations are necessary to achieve the desired performance in many real-time systems and digital image processing applications. In all these applications, one of the important arithmetic operations frequently performed is to multiply and accumulate with a small computational time (delay). As in all the arithmetic operations, it is the squaring which is most important in finding the transforms or the inverse transforms in signal processing. The squaring operation occupies most of the computing time; therefore, it becomes imperative to concentrate on improving the speed with which we square the numbers. The squaring operation also forms the backbone in cryptography. In this paper, we propose a technique for implementing squaring operation using Vedic methods in VHDL and evaluate the performance. The results are compared with the conventional Booth’s algorithm in terms of time delay and area occupied on the Xilinx Virtex 4vlx15sf363-12.

VLSI implementation of adders for high speed ALU

Abstract: This paper is primarily deals the construction of high speed adder circuit using Hardware Description Language (HDL) in the platform Xilinx ISE 9.2i and implement them on Field Programmable Gate Arrays (FPGAs) to analyze the design parameters. The motivation behind this investigation is that an adder is a very basic building block of Arithmetic Logic Unit (ALU) and would be a limiting factor in performance of Central Processing Unit (CPU). In the past, thorough examination of the algorithms with the respect to particular technology has only been partially done. The merit of the new technology is to be evaluated by its ability to efficiently implement the computational algorithms. In the other words, the technology is developed with the aim to efficiently serve the computation. The reverse path; evaluating the merit of the algorithms should also be taken. Therefore, it is important to develop computational structures that fit well into the execution model of the processor and are optimized for the current technology. In such a case, optimization of the algorithms is performed globally across the critical path of its implementation. In this research article, we have simulated and synthesized the various adders like full adder, ripple carry adder, carry-look ahead adder, carry-skip adder, carry — select adder and carry-save adder by using VHDL and Xilinx ISE 9.2i. The simulated results are verified and the functionality of high speed adders and the parameters like area and speed is analyzed. Finally this paper concludes that the carry-save adder is the more efficient in speed and area consumption.

Dynamic data folding with parameterizable FPGA configurations

Abstract: In many applications, subsequent data manipulations differ only in a small set of parameter values. Because of their reconfigurability, FPGAs (field programmable gate arrays) can be configured with a specialized circuit each time the parameter values change. This technique is called dynamic data folding. The specialized circuits are smaller and faster than their generic counterparts. However, the overhead involved in generating the configurations for the specialized circuits at runtime is very large when conventional tools are used, and this overhead will in many cases negate the benefit of using optimized configurations.This article introduces an automatic method for generating runtime parameterizable configurations from arbitrary Boolean circuits. These configurations, in which some of the configuration bits are expressed as a closed-form Boolean expression of a set of parameters, enable very fast run-time specialization, since specialization only involves evaluating these expressions. Our approach is validated on a ternary content-addressable memory (TCAM). We show that the specialized configurations, produced by our method use 2.82 times fewer LUTs than the generic configuration, and even 1.41 times fewer LUTs than the implementation generated by Xilinx Coregen. Moreover, while Coregen needs hand-crafted generators for each type of circuit, our toolflow can be applied to any VHDL design. Using our automatic and generally applicable method, run-time hardware optimization suddenly becomes feasible for a large class of applications.

An FPGA Implementation of the ZUC Stream Cipher

Abstract: In this paper a hardware implementation of ZUC stream cipher is presented. ZUC is a stream cipher that forms the heart of the 3GPP confidentiality algorithm 128-EEA3 and the 3GPP integrity algorithm 128-EIA3, offering reliable security services in Long Term Evolution networks (LTE). A detailed hardware implementation is presented in order to reach satisfactory performance results in LTE systems. The design was coded using VHDL language and for the hardware implementation, a XILINX Virtex-5 FPGA was used. Experimental results in terms of performance and hardware resources are presented.

FPGA design of a truncated SVD based receiver for the detection of SEFDM signals

Abstract: This work presents the hardware design of a novel algorithm using Field Programmable Gate Arrays (FPGAs) for the detection of Spectrally Efficient Frequency Division Multiplexing (SEFDM) signals. Previous work has shown that a sub-optimal Truncated Singular Value Decomposition (TSVD) approach is well-suited for use in SEFDM systems. TSVD offers a targeted reduction in complexity while outperforming linear detectors, such as Zero Forcing (ZF) and Minimum Mean Squared Error (MMSE), in terms of Bit Error Rate (BER). This is the first time a hardware design for the TSVD algorithm has been devised for implementation on an FPGA device using Very high speed integrated circuit Hardware Description Language (VHDL). Results show excellent fixed-point performance which are comparable to existing floating-point computer-based simulations. The optimal parameters required to achieve this outcome combined with their effect on system performance are identified. The impact of finite FPGA resources against performance gain is also examined.

An FPGA implementation of hard‐wired sequence control system based on PLC software

Abstract: Although a programmable logic controller (PLC) has been widely adopted for the sequence control of industrial machinery, its performance does not always satisfy the recent requirements in large and highly responsive systems. With the state-of-the-art field programmable gate array (FPGA) technology, it is possible to implement a control program with hard-wired logic for higher response and reduced implementation cost/space. This approach is also worthwhile for transmigration of legacy PLC software into forthcoming FPGA-based control hardware. This study presents a systematic method to implement a hard-wired sequence control from PLC software. PLC instructions are converted into VHDL codes, and then implemented as logic circuit with various peripheral functions. Productive PLC programs were examined with Mitsubishi Electric FX2N PLC and Altera Stratix II FPGA, and were shown to fit into a common FPGA chip. A straightforward Sequential design was estimated to be 184 times faster than PLC, while a performance-oriented Flat design was estimated to be 44 times faster than Sequential design (i.e., 8050 times faster than PLC). A practical perfect layer winder system was actually built and successfully operated with our FPGA control board, whose logic design was implemented with our tools. © 2011 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

Simulation and implementation of a BPSK modulator on FPGA

Abstract: The paper presents the simulation of a BPSK Modulator using Matlab/ Simulink environment and System Generator, a tool from Xilinx used for FPGA design as well as the implementation of the modulator on a Spartan 3E Starter Kit board. The modulator algorithm has been implemented on FPGA using the VHDL language on Xilinx ISE 12.3. The modulated signal obtained from simulations was compared with the signal obtained after implementation.

FPGA-based implementation of intelligent predictor for global solar irradiation, Part I: Theory and simulation

Abstract: Recent advances in artificial intelligent techniques embedded into a Field Programmable Gate Array (FPGA) allowed the application of such technologies in real engineering problems (robotic, image and signal processing, control, power electronics, etc), however, the application of such technologies in the solar energy field is very limited The embedded intelligent algorithm into FPGA can play a very important role in energy and renewable energy systems for control, monitoring, supervision, etc In this paper, the software as well as the implementation of intelligent predictors for solar irradiation on reconfigurable FPGA is described FPGA technology was employed due to its development, flexibility and low cost An experimental dataset of air temperature, solar irradiation, relative humidity and sunshine duration in a specific area is used; this database has been collected from 1998 to 2002 at Al-Madinah (Saudi Arabia) Initially, a MultiLayer Perceptron (MLP) is trained by using a set of 1460 patterns and then a set of 365 patterns are used for testing and validating the MLP-predictor Six MLP-predictors (configurations) are proposed and developed by varying the MLP inputs data, while the output is always the global solar irradiation for different configurations [[email protected]?(t,T,S,RH),[email protected]?(t,T,S),[email protected]?(t,T,RH),[email protected]?(t,S,RH)[email protected]?(t,T)[email protected]?(t,S)] Subsequently, the different MLP-predictors developed are written and simulated under the Very High Speed Integrated Circuit Hardware Description Language (VHDL) and ModelSim(R) The best designed architecture for different MLP-predictors is then implemented under the Xilinx(R) Virtex-II FPGA (XC2v1000) The developed hardware devices permit the prediction of global solar irradiation using available air temperature, relative humidity and sunshine duration; therefore, the designed configurations are very suitable especially in areas, where there are no instruments for measuring the solar irradiation data

A Novel Design for High Speed Multiplier for Digital Signal Processing Applications (Ancient Indian Vedic mathematics approach)

Abstract: In this paper, a high performance, high throughput and area efficient architecture of a multiplier for the Field Programmable Gate Array (FPGAs) is proposed. The most significant aspect of the proposed method is that, the developed multiplier architecture is based on vertical and crosswise structure of Ancient Indian Vedic Mathematics. As per The proposed architecture, for two 8-bit numbers; the multiplier and multiplicand, each are grouped as 4-bit numbers so that it decomposes into 4×4 multiplication modules. It is also illustrated that the further hierarchical decomposition of 4×4 modules into 2×2 modules will not have a significant effect in improvement of the multiplier efficiency or in other words multiplier decomposition nearly reaches a saturation level in its efficiency at 4×4 decomposition. The coding is done in VHDL (Very High Speed Integrated Circuits Hardware Description Language) and the FPGA synthesis is done using Xilinx library.