A
Abraham Mathews
Researcher at IBM
Publications - 19
Citations - 273
Abraham Mathews is an academic researcher from IBM. The author has contributed to research in topics: eDRAM & Dram. The author has an hindex of 8, co-authored 18 publications receiving 266 citations.
Papers
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Journal ArticleDOI
A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache
John E. Barth,Donald W. Plass,Erik A. Nelson,Chorng-Lii Hwang,Gregory J. Fredeman,Michael A. Sperling,Abraham Mathews,T. Kirihata,William Robert Reohr,K Nair,Nianzheng Caon +10 more
TL;DR: A 1.35 ns random access and 1.7 ns-random-cycle SOI embedded-DRAM macro has been developed for the POWER7™ high-performance microprocessor, allowing the embedded DRAM to operate reliably without constraining of the microprocessor voltage supply windows.
Patent
Peak power reduction methods in distributed charge pump systems
TL;DR: In this paper, a distributed charge pump system uses a delay element and frequency dividers to generate out of phase pump clock signals that drive different charge pumps, to offset peak current clock edges for each charge pump and thereby reduce overall peak power.
Proceedings ArticleDOI
A 45nm SOI embedded DRAM macro for POWER7TM 32MB on-chip L3 cache
John E. Barth,Don Plass,Erik A. Nelson,Charlie Hwang,Gregory J. Fredeman,Michael A. Sperling,Abraham Mathews,William Robert Reohr,Kavita Nair,Nianzheng Cao +9 more
TL;DR: This high performance DRAM macro is used to construct a large 32MB L3 cache on-chip, eliminating delay, area and power from the off-chip interface, simultaneously improving system performance, reducing cost, power and soft error vulnerability.
Patent
Switched-Capacitor Charge Pumps
TL;DR: In this article, a two-phase charging circuit, cross-coupled transistors connected to output nodes of the switched capacitors, and a pump output connected to source terminals of the transistors are described.
Journal ArticleDOI
A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS
Peter Juergen Klim,John E. Barth,William Robert Reohr,David Dick,Gregory J. Fredeman,Gary Koch,Hien Minh Le,A. Khargonekar,Pamela Wilcox,John W. Golz,Jente B. Kuang,Abraham Mathews,Jethro C. Law,Trong V. Luong,Hung C. Ngo,R. Freese,Hillery C. Hunter,Erik A. Nelson,Paul C. Parries,Toshiaki Kirihata,Subramanian S. Iyer +20 more
TL;DR: A single voltage supply, 1 MB cache subsystem prototype that integrates 2 GHz embedded DRAM (eDRAM) macros with on- chip word-line voltage supply generation, a 4 Kb one-time-programmable read-only memory (OTPROM) for redundancy and repair control, and on-chip OTPROM programming voltage generation, clock generation and distribution are described.